Device Electronics Based on nanoWires and NanoTubes

通过混合技术将具有弹道输运能力的cnfet和Si纳米线引入标准CMOS中，具有相当大的空间。目前阻碍该技术使用的主要原因是缺乏具有可预测器件特性的MOS类型配置的受控制造技术。要解决这个问题，需要足够的物理模型和仿真工具。合作研究涉及四个伙伴：1)比萨：具有接触的门控结构的弹道输运原子模型。(2)维也纳：包括散射在内的有效质量输运方法。(3)德蒙福特大学：剑桥制造器件的表征、参数提取和缺陷分析。这些参数将被输入比萨和维也纳的模型中。(4)剑桥大学：设备制造。该项目的总体目标是进行理论与实验相结合的综合分析，为未来此类技术的制造提供一些基本的设计规则。

There is considerable scope for CNFETs and Si Nanowires with their capability of ballistic transport, to be introduced into standard CMOS via a hybrid technology.The main reason currently hampering the use of this technology is an absence of controlled fabrication techniques in MOS type configurations with predictable device characteristics. Adequate physical models and simulation tools are necessary to address this issue.collaborative research involves four partners: 1) Pisa : Atomistic modelling of ballistic transport in gated structures with contacts. (2) Vienna: Effective mass approach to transport inclusive of scattering.(3) De Montfort University : Characterisation, parameter extraction and defect analysis of devices fabricated at Cambridge. The parameters will be fed into the modelling at Pisa and Vienna.(4) Cambridge University : Fabrication of devices.overall goal of the project is to carry out a comprehensive analysis linking theory with experiment to enable some fundamental design rules for fabrication of such technologies in future.