Topological Insulator based Transistors for Neuromorphic Computer Systems

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As dimensional scaling of CMOS is approaching fundamental limits, new information processing devices and micro-architectures are required to extend the capability of present-day Von-Neumann based computers. Application pulls for the new information age such as big data, Internet of Things (IoT), autonomous systems, exascale computing require artificial intelligence (AI) chips that can operate on super ultra-low power to ultimately match and exceed the efficiency of the human brain. A leading candidate for such low power computing architecture is the spiking neural network (SNN), which is one type of event-based learning without any external memory that consumes very little energy. However, the hardware component that emulates the decision-making process of a SNN - a neuron, consumes high power and therefore presently limits the performance of AI. This project brings together expertise from University of Glasgow and Sheffield to explore ternary Topological Insulator (Bi2Te2Se) as a low voltage material platform for a leaky integrate and fire neuron. By controlling the device surface states, the conductance of the channel will be tuned, sufficient enough to transmit a current spike from the drain to the source terminals. A successful demonstration of this concept will result in a milestone leap in hardware implementations of Artificial Neural Networks. The work is exciting and adventurous because there are only two reported TTI-FETs in the literature so far (from 2011and 2012 respectively), and neither of them is being envisaged to be operated as we plan in this work. Beyond the stated goals, new knowledge will be generated of interest to materials science, spintronics and quantum computing communities, where the knowledge gained from this project offers the potential to address existing bottlenecks in these research fields.