Energy Efficient Networks-on-Chip for Dynamically Reconfigurable Computing Platforms.

这项工作的目的是调查片上网络结构，将使未来的可重构计算系统集成数十或数百个处理瓦片实现嵌入式微处理器，知识产权的核心，可重构结构，专用本地存储器和DSP功能。可重配置的NoC结构将指导多个处理瓦片之间的有效通信和数据交换，并实现具有低延迟和低能耗的容错和非常高的通信带宽。处理瓦片将根据应用需求改变其功能和操作点。

The purpose of this work is to investigate an on-chip network fabric that will enable future reconfigurable computing systems integrating tens or hundreds of processing tiles implementing embedded microprocessors, intellectual property cores, reconfigurable fabrics, dedicated local memories and DSP functionality. The reconfigurable NoC fabric will direct the effective communication and exchange of data among the multiple processing tiles and enable fault-tolerance and very high communication bandwidths with low-latency and low energy consumption. The processing tiles will morph their functionality and operation point based on the application demands.