Secure Design Flow

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The importance of security is rapidly growing in traditional applications, such as payment and access control facilities, as well as in wireless computing, viz. mobile phones, set top boxes, PDA, heart monitors, alarms. Many electronics companies put large investments into the production of security-enhanced devices. For example, many international companies specialising in smart cards have strong interests in the area of circuit level security, as recent publication show.The overall aim of this project is to develop a set of design methods and tools for enhancing the use of industrial EDA tools in the context of developing hardware for secure systems using solutions that are based on higher radix optimization techniques. In this project we wish to explore a much broader range of solutions encompassing Galois Fields. We will study new methods for direct encoding in higher radices (using 1-of-n, m-of-n codes) for power-balancing and fault-tolerance and develop the synthesis flow around it. The enhanced language driven design flow should incorporate certain power efficient and area efficient synchronous and asynchronous techniques together with relevant low-power multi-valued logic mapping techniques. The new flow would not stipulate a specific architectural style or synthesis style for the entire system. In this way, our new approach could be characterised as the 'best-effort' design and synthesis of efficient secure logic at the asynchronous or synchronous level.The goal of the project, therefore, is a set of radically improved design methods and efficient tool support for constructing circuits for secure applications, such as smart card ICs, from behavioural descriptions in common HDLs, such as Verilog, VHDL, SystemC etc. The methodology will incorporate measures for applying higher-radix techniques to the development of secure circuits for enhancing power-balanced signatures and protection against fault-insertion. This will include the use of techniques such as delay-insensitive codes and code balancing.The key contributions of this work will be: (1) at the structural level, a set of RTL architectures developed at the higher radix level (using 1-of-n, m-of-n codes), primarily targetting low power, power-balanced and fault tolerant implementations, meeting a range of area, speed, power-balancing and fault-induction detection tradeoffs and supported by component libraries; (2) at the behavioural level, a complete security design flow based on higher radix scalable architectures, in which power-balancing and fault-tolerant aspects can be incorporated and supported by tools for translating from the HDLs into efficient control, datapath and interface logic. The results of (1) will be used as base building blocks to be used together with those that are already used in the current design practice. At the same time those under (2) will serve the goal of enhancing the current design flow, i.e. starting from the behavioural security descriptions and targetting more efficient higher-radix circuit implementations.The project will involve collaboration with a major smartcard company Atmel who will provide support on the experimental front and access to important case studies.