Globally Asynchronous Elastic Logic Synthesis (GAELS)
全局异步弹性逻辑综合(GAELS)
基本信息
- 批准号:EP/I038551/1
- 负责人:
- 金额:$ 49.4万
- 依托单位:
- 依托单位国家:英国
- 项目类别:Research Grant
- 财政年份:2011
- 资助国家:英国
- 起止时间:2011 至 无数据
- 项目状态:已结题
- 来源:
- 关键词:
项目摘要
This project will develop an integrated theoretical and practical foundation for new methods and CAD tools to support the design of various types of systems with mixed synchronous-asynchronous operation. The crucial novelty will be in the use of the Elastic Logic principles when arranging interaction between blocks, partitioning the system into multi-block components ('localities').It will for the first time provide a pragmatic way of automating the design of mixed synchronous-asynchronous systems with varying granularity level, thereby leading to the development and application of systematic optimization techniques to obtain solutions targeted at the key design issues for deep submicron DSM and 3D implementation technologies, such as process variation power dissipation, area and speed.The project will deliver new theoretical models and algorithms for data-flow representation of systems for timing and power elasticity, automated partitioning of globally synchronous systems into subsystems with local synchronism, automated conversion of systems to elastic form and introduction of asynchronous protocols, design of synchronous-asynchronous interfaces and integration of the new methods into an appropriate industrial CAD environment. The new methods will be tested using an advanced case study from the industrial collaborators, using an advanced DSM technology.
本计划将为新方法和CAD工具提供综合的理论和实践基础,以支持设计各种类型的混合同步-异步操作系统。关键的新颖性将是在安排块之间的交互时使用弹性逻辑原则,将系统划分为多块组件(“位置”)。它将首次为不同粒度级别的混合同步-异步系统的自动化设计提供一种实用的方法,从而导致系统优化技术的发展和应用,以获得针对深亚微米DSM和3D实现技术的关键设计问题的解决方案,如工艺变化功耗,面积和速度。该项目将为时序和功率弹性系统的数据流表示提供新的理论模型和算法,将全局同步系统自动划分为具有局部同步的子系统,将系统自动转换为弹性形式并引入异步协议,设计同步-异步接口,并将新方法集成到适当的工业CAD环境中。新方法将使用来自工业合作者的先进案例研究,使用先进的DSM技术进行测试。
项目成果
期刊论文数量(10)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
A Structured Visual Approach to GALS Modeling and Verification of Communication Circuits
- DOI:10.1109/tcad.2016.2611508
- 发表时间:2017-06
- 期刊:
- 影响因子:2.9
- 作者:F. Burns;D. Sokolov;A. Yakovlev
- 通讯作者:F. Burns;D. Sokolov;A. Yakovlev
Elastic bundles : modelling and architecting asynchronous circuits with granular rigidity
- DOI:
- 发表时间:2017
- 期刊:
- 影响因子:0
- 作者:Johnson Fernandes
- 通讯作者:Johnson Fernandes
Subthreshold-based m-sequence code generator for ultra low-power body sensor nodes
用于超低功耗人体传感器节点的基于亚阈值的 m 序列代码生成器
- DOI:10.1109/patmos.2016.7833686
- 发表时间:2016
- 期刊:
- 影响因子:0
- 作者:Abdulfattah A
- 通讯作者:Abdulfattah A
Persistent and Nonviolent Steps and the Design of GALS Systems
持久和非暴力步骤以及 GALS 系统的设计
- DOI:10.3233/fi-2015-1173
- 发表时间:2015
- 期刊:
- 影响因子:0.8
- 作者:Lukasz Mikulski;Marta Pietkiewicz-Koutny;Danil Sokolov;Alex Yakovlev
- 通讯作者:Alex Yakovlev
Concurrent Multiresource Arbiter: Design and Applications
并发多资源仲裁器:设计与应用
- DOI:10.1109/tc.2011.218
- 发表时间:2013
- 期刊:
- 影响因子:3.7
- 作者:Golubcovs S
- 通讯作者:Golubcovs S
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Alexandre Yakovlev其他文献
Improved parameterized efficient FPGA implementations of parallel 1-D filtering algorithms using Xilinx System Generator
使用 Xilinx System Generator 改进并行一维滤波算法的参数化高效 FPGA 实现
- DOI:
- 发表时间:
2010 - 期刊:
- 影响因子:0
- 作者:
S. Hasan;S. Boussakta;Alexandre Yakovlev - 通讯作者:
Alexandre Yakovlev
Implementations of Parallel l-D Filtering Algorithms Using Xilinx System Generator
使用 Xilinx System Generator 实现并行 l-D 滤波算法
- DOI:
- 发表时间:
2011 - 期刊:
- 影响因子:0
- 作者:
S. Hasan;Alexandre Yakovlev - 通讯作者:
Alexandre Yakovlev
REPUTE: An OpenCL based Read Mapping Tool for Embedded Genomics
REPUTE:基于 OpenCL 的嵌入式基因组读取映射工具
- DOI:
- 发表时间:
2020 - 期刊:
- 影响因子:0
- 作者:
Sidharth Maheshwari;R. Shafik;Ian Wilson;Alexandre Yakovlev;A. Acharyya - 通讯作者:
A. Acharyya
PLEDGER: Embedded Whole Genome Read Mapping using Algorithm-HW Co-design and Memory-aware Implementation
PLEDGER:使用算法硬件协同设计和内存感知实现的嵌入式全基因组读取映射
- DOI:
- 发表时间:
2021 - 期刊:
- 影响因子:0
- 作者:
Sidharth Maheshwari;R. Shafik;Ian Wilson;Alexandre Yakovlev;Venkateshwarlu Y. Gudur;A. Acharyya - 通讯作者:
A. Acharyya
Energy-efficient approximate wallace-tree multiplier using significance-driven logic compression
使用重要性驱动逻辑压缩的节能近似华莱士树乘法器
- DOI:
10.1109/sips.2017.8109990 - 发表时间:
2017 - 期刊:
- 影响因子:0
- 作者:
Issa Qiqieh;R. Shafik;Ghaith Tarawneh;D. Sokolov;Shidhartha Das;Alexandre Yakovlev - 通讯作者:
Alexandre Yakovlev
Alexandre Yakovlev的其他文献
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{{ truncateString('Alexandre Yakovlev', 18)}}的其他基金
UKRI-RCN: Exploiting the dynamics of self-timed machine learning hardware (ESTEEM)
UKRI-RCN:利用自定时机器学习硬件(ESTEEM)的动态
- 批准号:
EP/X039943/1 - 财政年份:2023
- 资助金额:
$ 49.4万 - 项目类别:
Research Grant
A4A: Asynchronous design for analogue electronics
A4A:模拟电子器件的异步设计
- 批准号:
EP/L025507/1 - 财政年份:2014
- 资助金额:
$ 49.4万 - 项目类别:
Research Grant
Staying alive in variable, intermittent, low-power environments (SAVVIE)
在多变、间歇性、低功耗环境中保持活力 (SAVVIE)
- 批准号:
EP/K012908/1 - 财政年份:2013
- 资助金额:
$ 49.4万 - 项目类别:
Research Grant
Dream Fellowship: Energy-Modulated Computing
梦想奖学金:能量调制计算
- 批准号:
EP/J005177/1 - 财政年份:2011
- 资助金额:
$ 49.4万 - 项目类别:
Research Grant
Reliable cell design methods for variable processes (RelCel)
适用于可变过程的可靠单元设计方法 (RelCel)
- 批准号:
EP/G066361/1 - 财政年份:2009
- 资助金额:
$ 49.4万 - 项目类别:
Research Grant
Next Generation Energy-Harvesting Electronics - holistic approach 1763
下一代能量收集电子设备 - 整体方法 1763
- 批准号:
EP/G066728/1 - 财政年份:2009
- 资助金额:
$ 49.4万 - 项目类别:
Research Grant
Side-channel Resistant Cryptographic IP for Smartcards
用于智能卡的抗侧信道加密 IP
- 批准号:
EP/G005273/1 - 财政年份:2008
- 资助金额:
$ 49.4万 - 项目类别:
Research Grant
Support for the 14th International Symposium on Asynchronous Circuits and Systems (ASYNC) and 2nd International Symposium on Networks on Chip (NOCS)
支持第十四届异步电路与系统国际研讨会 (ASYNC) 和第二届片上网络国际研讨会 (NOCS)
- 批准号:
EP/F029012/1 - 财政年份:2008
- 资助金额:
$ 49.4万 - 项目类别:
Research Grant
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