Self-Timed Event Processor

自定时事件处理器

• 批准号: EP/E044662/1
• 负责人: Alexandre Yakovlev
• 金额: $ 47.39万
• 依托单位: Newcastle University
• 依托单位国家: 英国
• 项目类别: Research Grant
• 财政年份: 2007
• 资助国家: 英国
• 起止时间: 2007 至 无数据
• 项目状态: 已结题
• 来源: https://gtr.ukri.org/projects?ref=EP%2FE044662%2F1
• 关键词: Self; Timed; Event; Processor

The field of this research is the design, synthesis and verification of asynchronous and reactive event handling and processing hardware. This hardware is expected to work in an environment of concurrent, distributed, and real-time computation networks. These networks include both truly distributed systems such as wireless networking, sensor networks, and real-time networks as well as highly integrated on-chip networked computers with distributed processing. These systems are becoming more complex, and the traffic among the processing elements is increasing. Therefore handling the events which make up the traffic may determine much of the system performance and characteristics. Both asynchrony and non-determinism are inevitable for computation networks in the future, firstly because of the different timing requirements of different and diverse functional elements. Secondly, concurrent and distributed system implementations lead to greater asynchrony and non-determinism as semiconductor technology advances and the degree of integration increases (the International Technology Roadmap for Semiconductors (ITRS-05) Design document emphasizes multiple clock domains and source-synchronous signalling, and predicts networks of self-timed blocks). Existing methods of designing event-handling systems in hardware are rather ad hoc and have no systematic modelling and synthesis support.From this point of view, the project proposed here may have a major impact on the industrial as well as academic community. We aim to develop a design and synthesis method for self-timed hardware subsystems (called self-timed event processors or STEPs). STEPs will handle events arriving asynchronously and non-deterministically from multiple sources, and respond (such as by allocating resources, whose availability may also be asynchronously and non-deterministically changing) according to user specifications. Self-timing is in the sense that the triggering information is derived from the signals representing the events themselves, and STEPs may be used to form virtual self-timed reactive service blocks with off the shelf service IP cores such as processors or communications devices. We propose that this method will include a general STEP architecture, techniques for deriving wire delay aware designs for the integral parts of the architecture, and techniques for verifying such designs. A general mathematical modelling technique for STEPs at all levels of detail based on Petri nets will form the basis for the design/synthesis and verification work. We aim to develop the design and synthesis techniques to a degree where the process becomes systematic, highly algorithmic, and potentially automatic, and will cover all levels of detail down to hardware gate level schematics. It is our view that STEP technology will be a step forward in the event handling front, and will help towards the realization of systems of self-timed blocks envisioned in ITRS-05.The project will involve as a collaborator MBDA UK Ltd, a leading European privider of design technology for real-time distributed systems for missile control. The company has pioneered the Butler (awarded with The Queed's Award for Enterpise 2004) and Route-Table technologies, which provide stimulating starting ideas for STEP, such as tiled circuit architecture.

本文研究的领域是异步和响应式事件处理和处理硬件的设计、综合和验证。这种硬件有望在并发、分布式和实时计算网络的环境中工作。这些网络既包括真正的分布式系统，如无线网络、传感器网络和实时网络，也包括具有分布式处理的高度集成的片上网络计算机。这些系统正变得越来越复杂，处理元素之间的流量也在增加。因此，处理构成流量的事件可能会决定系统的大部分性能和特征。在未来的计算网络中，异步和不确定性是不可避免的，首先是因为不同功能元素对时间的要求不同。其次，随着半导体技术的进步和集成程度的提高，并发和分布式系统实现导致更大的异步和非确定性（国际半导体技术路线图（ITRS-05）设计文件强调多个时钟域和源同步信号，并预测自定时块网络）。现有的在硬件上设计事件处理系统的方法是相当特殊的，没有系统的建模和综合支持。从这个角度来看，这里提出的项目可能会对工业界和学术界产生重大影响。我们的目标是开发一种自定时硬件子系统（称为自定时事件处理器或STEPs）的设计和合成方法。STEPs将处理来自多个源的异步和非确定性到达的事件，并根据用户规范进行响应（例如通过分配资源，其可用性也可能是异步和非确定性变化的）。自定时是指触发信息来自表示事件本身的信号，STEPs可用于与现成的服务IP核（如处理器或通信设备）形成虚拟的自定时响应服务块。我们建议该方法将包括一个通用的STEP体系结构，为该体系结构的组成部分推导线延迟感知设计的技术，以及验证此类设计的技术。基于Petri网的所有细节级别步骤的通用数学建模技术将构成设计/综合和验证工作的基础。我们的目标是开发设计和合成技术，使过程变得系统化，高度算法化，并可能自动化，并将涵盖所有级别的细节，直至硬件门级原理图。我们认为STEP技术将在事件处理方面向前迈进一步，并将有助于实现ITRS-05中设想的自定时块系统。该项目将与欧洲领先的导弹控制实时分布式系统设计技术供应商MBDA英国有限公司合作。该公司率先推出了管家（荣获2004年企业奖）和Route-Table技术，为STEP提供了刺激的启动想法，例如平铺电路架构。

项目成果

Run-time Configurable Approximate Multiplier using Significance-Driven Logic Compression

使用显着性驱动逻辑压缩的运行时可配置近似乘法器

• DOI: 10.1109/iccd53106.2021.00029
• 发表时间: 2021
• 作者: Haddadi I

Concurrent Multiresource Arbiter: Design and Applications

并发多资源仲裁器：设计与应用

• DOI: 10.1109/tc.2011.218
• 发表时间: 2013
• 期刊: IEEE Transactions on Computers
• 影响因子: 3.7
• 作者: Golubcovs S

Multi-resource approach to asynchronous SoC : design and tool support

• 发表时间: 2011
• 作者: Stanislavs Golubcovs

Statistical analysis of crosstalk-induced errors for on-chip interconnects

• DOI: 10.1049/iet-cdt.2009.0054
• 发表时间: 2011-03
• 期刊: IET Comput. Digit. Tech.
• 作者: Basel Halak;A. Yakovlev

Generalised Asynchronous Arbiter

广义异步仲裁器

• DOI: 10.1109/acsd.2019.00005
• 发表时间: 2019
• 作者: Golubcovs S