DEVELOPMENT OF PULSED & FT ESR SPECTROMETER TIMING

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This subproject is one of many research subprojects utilizing the resources provided by a Center grant funded by NIH/NCRR. The subproject and investigator (PI) may have received primary funding from another NIH source, and thus could be represented in other CRISP entries. The institution listed is for the Center, which is not necessarily the institution for the investigator. The timing system is a central component of a pulsed ESR spectrometer. A FT-ESR spectrometer featuring nanosecond pulses requires picosecond level pulse stability and timing resolution. Only one highly-priced model of a delay generator of modular type featuring such resolution and moderately fast reprogram ability is available commercially. Several such units would be necessary for a complete system, and modules necessary for system integration would have to be designed in-house. For this reason, we designed and built a complete low-cost system, tailored for pulsed and FT-ESR spectroscopy. Our efforts are well in-line with modern trends, which follow a system-on-a-chip design approach. The latest version of our timing hardware is residing in FPGA (field-programmable gate array) and is controlled in real time with SHARC DSP with the capability of updating a pulse sequence in 20 micro s or faster. This is a prerequisite for 1D or 2D acquisition ¿in real time¿ required in stopped-flow or continuous flow kinetic experiments wherein the whole experiment takes a few seconds. This would require writing special DSP code in order to synchronize the whole process of rapid data collection with the averaging ADC, residing in the host. The critical timing hardware resides in FPGA, clocked at 125 MHz, thus providing 8 ns timing resolution. A further resolution improvement down to 10 ps is provided by means of low-voltage ECL circuitry for 8 pulses, 1 trigger channel, and 2 lines for TWTA fine gating. The timing system thus has 11 channels of fine timing. There are additional output channels: four lines for phase control and 4 lines with 8 ns resolution for less demanding tasks such as TWTA coarse gating. This system, which is the second design iteration of the 50 ps resolution prototype system, has smaller form-factor and considerably reduced power consumption (a factor of 4), drawing less than 6A from a 3.3 V source.