Visualization systems for FPGA architectures and CAD algorithms

适用于 FPGA 架构和 CAD 算法的可视化系统

• 批准号: 344569-2007
• 负责人: Lemieux, Guy
• 金额: $ 2.95万
• 依托单位: University of British Columbia
• 依托单位国家: 加拿大
• 项目类别: Research Tools and Instruments - Category 1 (<$150,000)
• 财政年份: 2006
• 资助国家: 加拿大
• 起止时间: 2006-01-01 至 2007-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=326125
• 关键词: Visualization; systems; FPGA; architectures; CAD

Large non-recurring engineering (NRE) fees of $10 million+ are a significant barrier to entry for small and mid-sized Canadian companies that hope to develop hardware-based products. These barriers are shattered by Field-Programmable Gate Arrays (FPGAs), a type of universal microchip. An FPGA can be configured to implement any digital circuit, without the need for an expensive chip-fabrication plant.  This flexibility, however, results in overhead that limits capacity, speed, and power.  This overhead is dramatically reduced by building FPGAs with advanced integrated circuit technology down to 22nm. While current industrial FPGA research and development is heavily focused on the next-available semiconductor process based on 65nm technology, academic research should be looking further ahead, namely at 45nm to 22nm technologies.  According to the 2005 International Technology Roadmap for Semiconductors (ITRS), these will be available in 2010 and 2016, or 4 and 10 years from now. In this research, we are investigating new architectures and algorithms for future FPGAs. Next-generation FPGAs will have much higher logic capacity and run at higher clock speeds than current FPGAs, enabling many new emerging applications. They will also require significantly different architectures and faster associated Computer-Aided Design algorithms because current approaches do not scale well. Current commercial 65nm CAD tools take hours or days to find a routing solution; this is unacceptable at 22nm where FPGAs will be roughly 10x larger. In addition, solving the interconnect routing problem requires a huge amount of memory because every wire and every switch (i.e., every multiplexer input) needs to keep significant state information throughout the algorithm. Visualization workstations with large memory capacity are required to pursue research into FPGA architecture and CAD algorithms at the 22nm semiconductor technology node.

1000万美元以上的大型非经常性工程（NRE）费用是希望开发基于硬件产品的中小型加拿大公司进入市场的重大障碍。现场可编程门阵列（FPGA）是一种通用微芯片，它打破了这些障碍。FPGA可以配置为实现任何数字电路，而不需要昂贵的芯片制造工厂。然而，这种灵活性会导致限制容量，速度和功耗的开销。通过使用先进的集成电路技术构建22 nm的FPGA，可以大大降低这种开销。虽然目前的工业FPGA研究和开发主要集中在基于65纳米技术的下一代半导体工艺上，但学术研究应该看得更远，即45纳米至22纳米技术。根据2005年国际半导体技术路线图（ITRS），这些技术将在2010年和2016年，或从现在起的4年和10年内推出。在这项研究中，我们正在研究未来FPGA的新架构和算法。下一代FPGA将具有比当前FPGA更高的逻辑容量，并以更高的时钟速度运行，从而实现许多新兴应用。它们还需要显著不同的架构和更快的相关计算机辅助设计算法，因为当前的方法不能很好地扩展。目前的商用65纳米CAD工具需要数小时或数天才能找到布线解决方案;这在22纳米时是不可接受的，因为FPGA大约要大10倍。此外，解决互连路由问题需要大量的存储器，因为每一根导线和每一个开关（即，每个多路复用器输入）需要在整个算法中保持重要的状态信息。在22纳米半导体技术节点上，需要具有大存储容量的可视化工作站来研究FPGA架构和CAD算法。