Visualization systems for FPGA architectures and CAD algorithms

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Large non-recurring engineering (NRE) fees of $10 million+ are a significant barrier to entry for small and mid-sized Canadian companies that hope to develop hardware-based products. These barriers are shattered by Field-Programmable Gate Arrays (FPGAs), a type of universal microchip. An FPGA can be configured to implement any digital circuit, without the need for an expensive chip-fabrication plant.  This flexibility, however, results in overhead that limits capacity, speed, and power.  This overhead is dramatically reduced by building FPGAs with advanced integrated circuit technology down to 22nm. While current industrial FPGA research and development is heavily focused on the next-available semiconductor process based on 65nm technology, academic research should be looking further ahead, namely at 45nm to 22nm technologies.  According to the 2005 International Technology Roadmap for Semiconductors (ITRS), these will be available in 2010 and 2016, or 4 and 10 years from now. In this research, we are investigating new architectures and algorithms for future FPGAs. Next-generation FPGAs will have much higher logic capacity and run at higher clock speeds than current FPGAs, enabling many new emerging applications. They will also require significantly different architectures and faster associated Computer-Aided Design algorithms because current approaches do not scale well. Current commercial 65nm CAD tools take hours or days to find a routing solution; this is unacceptable at 22nm where FPGAs will be roughly 10x larger. In addition, solving the interconnect routing problem requires a huge amount of memory because every wire and every switch (i.e., every multiplexer input) needs to keep significant state information throughout the algorithm. Visualization workstations with large memory capacity are required to pursue research into FPGA architecture and CAD algorithms at the 22nm semiconductor technology node.