ANR_Single electron device integration on CMOS technology (Joint research project with Agence National de Recherche, France)

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Since the creation of the integrated circuit, more than 4 decades ago, a tenfold increase in computing performance has been achieved every 5 years. The most significant impact of this trend is the continuing decrease of cost-per-chip which has led to significant improvement in economic productivity and overall quality of life though the proliferation of computers, communication and electronics in general. This outstanding improvement is essentially due to the scaling down of the CMOS technology (Complementary Metal Oxide Semiconductor). The aim of this project is not to replace CMOS circuits for general purpose Boolean logic but rather to develop enhanced CMOS technology by adding new functionalities through heterogeneous integration of new nanodevices. The objective of this project consists in stacking Single Electron Devices (SED) (transistors or memories) on existing CMOS technology and providing the tools to make use of such hybrid SED-CMOS technology. The advantages of such an approach are numerous and address major concerns of the industry: larger integration density (3-D vs 2-D), reduced interconnect lengths (to overcome SED fan-out issues), non invasive technology (CMOS fabrication process is not disturbed). This project is presented by a consortium of researchers from the Center of Excellence in Information Engineering at Universite de Sherbrooke, the Laboratory for Micro and Nanofabrication at INRS- Energy, Materials and Telecommunications, Lyon Institute of Nanotechnology at INSA-Lyon in France,