Emerging devices integration above CMOS circuit

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During the last 5 decades, the microelectronic industry has been able to drastically increase the computing performance while reducing the cost-per-chip. This outstanding improvement is essentially due to the scaling of the CMOS (Complementary Metal Oxide Semiconductor) technology. The International Technology Roadmap for Semiconductors (ITRS) anticipates that this trend or his equivalent in performance will continue for several years resulting ultimately in 5-7 nm gate transistors by 2025. This projection challenges the most optimistic prediction of transistor utilizing the CMOS physics for operation. Thus, innovative solutions must be introduced for post-CMOS technology in the midterm. Furthermore, the power density tendency of assembled modules is reaching level where standard air cooling is not adequate anymore. This energy consumption issue is becoming the predominant factor for introducing new devices. The industry is pursing different approaches for post-CMOS and equivalent performance enhancement. One solution for the former issue is the introduction of the very promising tunnel field effect transistor. For the latter one, tremendous effort have been deployed to increase the number of device by mm2 through 3D integration at the chip level. This proposed research program will address both issues by investigating innovative low-power nanoelectronics device that can be monolithically integrated in 3D with CMOS technology to investigate new functionalities and increase performance of logic and memory devices. The global objective is not to directly replace CMOS technology but rather complement it using back-end-of-line compatible devices. Such approach allows to i) increase devices density due to 3D integration, ii) reduce latency from shorter interconnections, iii) globally reduce energy consumption by reducing parasitic loss. During this 5 years project, we will develop two low-power nanoelectronic devices integrated above CMOS circuit. The silicon nanocrystal tunnel field effect transistor combines our nanodamascene process and amorphous silicon. The potential outcome of such device will be the realization of a low-power transistor operating at voltage below 0.5V with extremely low Ioff current due to tunneling through undoped channel. The second nanoelectronic device will also combine our nanodamascene process with indium oxide nanocrystals to realize embedded non-volatile memory. This two terminals memory has the advantage to be highly scalable and the potential to be embedded with microprocessor. The scientific and social impact of this research is ranging from more energy efficient portable electronic (tablet, smart phone) to universal memory (single memory type regrouping DRAM, hard-disk and flash memory).