Raising the Abstraction of Analysis, Debug and Optimization of High-Level Synthesis-Generated Hardware

提高高级综合生成硬件分析、调试和优化的抽象性

• 批准号: 447002-2013
• 负责人: Wilton, Steven
• 金额: $ 7.22万
• 依托单位: University of British Columbia
• 依托单位国家: 加拿大
• 项目类别: Strategic Projects - Group
• 财政年份: 2014
• 资助国家: 加拿大
• 起止时间: 2014-01-01 至 2015-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=554498
• 关键词: Raising; Abstraction; Analysis; Debug; Optimization

Unprecedented advances in Integrated Circuit fabrication technology have given rise to the low-cost high-speed Internet, mobile computing, and unparalleled computing power that analyzes, manipulates and automates activity throughout the planet. As integration continues its exponential progress, however, the complexity of the underlying fabrication technology, the expertise required to exploit it, and the financial risk associated with each deployment has also grown at an exponential rate. Field-Programmable Gate Arrays (FPGAs) have emerged as a Programmable Platform of choice for many of these crucial applications. FPGAs can be configured to implement any circuit, allowing designers to immediately test designs without the cost, risk and delay of producing a fully-customized chip.

集成电路制造技术的空前进步催生了低成本的高速互联网、移动的计算以及无与伦比的计算能力，这些计算能力可以分析、操纵和自动化整个地球的活动。 然而，随着集成继续呈指数级增长，底层制造技术的复杂性、利用它所需的专业知识以及与每次部署相关的财务风险也以指数级速度增长。 现场可编程门阵列（FPGA）已成为许多这些关键应用的可编程平台的选择。 FPGA可以配置为实现任何电路，允许设计人员立即测试设计，而无需生产完全定制的芯片的成本，风险和延迟。