Bringing Field-Programmable Gate Arrays to the Masses: Towards a Design Eco-System

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For decades, improvements in integrated circuit (IC) technology have provided dramatic increases in computing power, enabling applications such as the low-cost high-speed internet and mobile computing. New applications are on the horizon, including embedded machine-learning algorithms, extreme “big data” computation problems, and applications associated with the emerging internet of things. However, advances in many of these important applications are being held back by the lack of sufficient power-efficient and cost-effective computing hardware capabilities. Due to the increased cost and technical challenges in manufacturing smaller and faster transistors, we can no longer rely on improvements in semiconductor technology to provide the required computing horsepower. This has led to a revolution in the computing industry. Many researchers now see hardware accelerators, and in particular accelerators based on Field-Programmable Gate Arrays (FPGAs), as a disruptive technology that can provide power-efficient computing capacity necessary for many of these emerging applications. For years, FPGAs have been extremely successful as low-cost, low-risk replacements for custom integrated circuits. However, as evidenced by Intel's recent acquisition of Altera, and Microsoft's efforts to bring FPGA technology to the “cloud”, FPGAs are now poised to emerge as mainstream software accelerators.*** Before FPGAs can evolve into this new role, critical challenges must be addressed. Hardware accelerators will only become ubiquitous if they can be designed, optimized, and debugged by software designers and domain experts. There has been significant effort developing high-level synthesis compilers which convert software code to a hardware design. However, a compiler is not enough. Software designers expect an entire eco-system which provides the ability to characterize, evaluate, optimize and iterate on their designs quickly. The proposed Discovery Grant project will be the backbone of a research program aimed at making FPGA acceleration accessible to software designers, by making such an ecosystem a reality. Specifically, the research will focus on three aspects: (1) an iterative design flow that brings the benefits of agile methodologies to hardware design, (2) improved core compilation technologies, and (3) improved device architectures. Together, these efforts will help make ubiquitous hardware acceleration a reality, enabling many emerging applications that are simply not feasible today.