Memory footprint and run-time scalability for FPGA CAD algorithms

在这个项目中，我们将研究提高将电路映射到现场可编程门阵列（fpga）的计算机辅助设计工具的可扩展性的方法。现场可编程门阵列为各种数字电路提供了低风险、低成本的实现路径。为了将电路映射到这些设备上，工程师们使用了一套编译工具。这些工具需要大量的计算资源，特别是在将电路映射到最先进的fpga时。随着fpga容量的增长，这个问题将变得更加严重。除非FPGA CAD工具的可扩展性得到解决，否则长时间运行和大内存占用将成为未来FPGA扩展的障碍，导致使用这些设备的公司增加成本和设计时间。

In this project, we will investigate methods of improving the scalability of computer-aided design tools that map circuits to Field-Programmable Gate Arrays (FPGAs). Field-Programmable Gate Arrays provide a low-risk, low-cost implementation path for a wide variety of digital circuits. To map circuits to these devices, engineers employ a suite of compilation tools. These tools require significant computing resources, especially when mapping circuits to state-of-the-art FPGAs. As the capacity of FPGAs grow, the problem will become even more severe. Unless the scalability of FPGA CAD tools is addressed, the long run times and large memory footprints will become a hindrance to future FPGA scaling, leading to increased costs and design times for companies which use these devices.