Fundamentals and Applications of Self-Assembly of Block Copolymer Nanostructures on Surfaces

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Self-assembled nanostructures continue to be the focus of intense research due to their obvious inspiration from Nature, and secondly, their enormous utility for patterning nanoscale structures with little outside intervention. The challenge lies in fabricating large areas of high density metallic and molecular nanostructures, with feature sizes below 20 nm, in an economically feasible manner for a broad swath of applications. While photolithography will justifiably remain a core technology with respect to the upcoming 22 nm generation in the computer industry, cost considerations for mass manufacturing, particularly with regards to lithography, remains the primary constraint for the sub-22 nm era. As a result, there is very strong interest in the development of complementary patterning strategies that involve large scale self-assembly, in which a soft organic template carries out the “hard work”, spontaneously forming nanoscale assemblies in a rapid and predictable fashion. In this proposed program, we will outline our approaches towards the use of self-assembled block copolymer (BCP) nanostructures on technologically relevant semiconductor materials, to produce sub 20-nm features. The International Roadmap for Semiconductors (ITRS, www.itrs.net, Emerging Research Materials chapter) refers to BCPs as a possible 'innovative technology' for application in some lithographic applications, but many challenges remain. For instance, the natural (or native) spacing of most BCP features is larger than 10 nm, as smaller polymer molecular weights may not phase segregate, and in other cases, BCP self-assembly is far too slow to use commercially. In order to improve both of these constraints, and others related to minimizing the error rate in BCP self-assembly, we will pursue two major projects, as described below. The first project of this program will address the one of the major challenges facing the application of BCP self-assembly within the semiconductor industry, and more broadly for a host of other applications, including biomedical problems. As stated in the International Roadmap for Semiconductors, faster annealing and self-assembly is required to reach commercialization; in the most recent version (2011) of the ITRS, our work using microwave annealing was cited as a possible route to address this concern. As yet, however, little is understood from both a fundamental perspective, and within the context of integration within a silicon (or other material) fabrication process. We propose to address the very shallow understanding related to the microwave process through detailed in-situ studies, to extend the use of microwaves to enable BCP annealing to materials that do not heat upon microwave irradiation, and to introduce a new and useful means to pattern the BCP assemblies using microwave-sensitive templates that will induce very localized heating, and hence annealing. The second project of the program focuses upon a dramatic reduction of the defect densities of BCP assemblies, with the stated ITRS goal of less than one defect per 0.01 cm2, while simultaneously decreasing feature spacings to below 10 nm. To accomplish these goals, we propose to use our density doubling approach recently published, with blends of BCPs. The density doubling decreases the natural spacing, or pitch, of self-assembled BCP features by a factor of two. Using our in-house algorithm to calculate defect densities, we will rapidly screen these density doubled BCP blends, identify key leads, and optimize these leads. We hope that this approach will enable the production of very small, sub-20 nm features, with low defect densities, with very smooth topologies (ie, with low line edge roughnesses).