Fundamentals and Applications of Self-Assembly of Block Copolymer Nanostructures on Surfaces

嵌段共聚物纳米结构表面自组装的基础与应用

• 批准号: RGPIN-2014-05195
• 负责人: Buriak, Jillian
• 金额: $ 7.29万
• 依托单位: University of Alberta
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2017
• 资助国家: 加拿大
• 起止时间: 2017-01-01 至 2018-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=632282
• 关键词: Fundamentals; Applications; Self; Assembly; Block

Self-assembled nanostructures continue to be the focus of intense research due to their obvious inspiration from Nature, and secondly, their enormous utility for patterning nanoscale structures with little outside intervention. The challenge lies in fabricating large areas of high density metallic and molecular nanostructures, with feature sizes below 20 nm, in an economically feasible manner for a broad swath of applications. While photolithography will justifiably remain a core technology with respect to the upcoming 22 nm generation in the computer industry, cost considerations for mass manufacturing, particularly with regards to lithography, remains the primary constraint for the sub-22 nm era. As a result, there is very strong interest in the development of complementary patterning strategies that involve large scale self-assembly, in which a soft organic template carries out the “hard work”, spontaneously forming nanoscale assemblies in a rapid and predictable fashion. In this proposed program, we will outline our approaches towards the use of self-assembled block copolymer (BCP) nanostructures on technologically relevant semiconductor materials, to produce sub 20-nm features. The International Roadmap for Semiconductors (ITRS, www.itrs.net, Emerging Research Materials chapter) refers to BCPs as a possible 'innovative technology' for application in some lithographic applications, but many challenges remain. For instance, the natural (or native) spacing of most BCP features is larger than 10 nm, as smaller polymer molecular weights may not phase segregate, and in other cases, BCP self-assembly is far too slow to use commercially. In order to improve both of these constraints, and others related to minimizing the error rate in BCP self-assembly, we will pursue two major projects, as described below. The first project of this program will address the one of the major challenges facing the application of BCP self-assembly within the semiconductor industry, and more broadly for a host of other applications, including biomedical problems. As stated in the International Roadmap for Semiconductors, faster annealing and self-assembly is required to reach commercialization; in the most recent version (2011) of the ITRS, our work using microwave annealing was cited as a possible route to address this concern. As yet, however, little is understood from both a fundamental perspective, and within the context of integration within a silicon (or other material) fabrication process. We propose to address the very shallow understanding related to the microwave process through detailed in-situ studies, to extend the use of microwaves to enable BCP annealing to materials that do not heat upon microwave irradiation, and to introduce a new and useful means to pattern the BCP assemblies using microwave-sensitive templates that will induce very localized heating, and hence annealing. The second project of the program focuses upon a dramatic reduction of the defect densities of BCP assemblies, with the stated ITRS goal of less than one defect per 0.01 cm2, while simultaneously decreasing feature spacings to below 10 nm. To accomplish these goals, we propose to use our density doubling approach recently published, with blends of BCPs. The density doubling decreases the natural spacing, or pitch, of self-assembled BCP features by a factor of two. Using our in-house algorithm to calculate defect densities, we will rapidly screen these density doubled BCP blends, identify key leads, and optimize these leads. We hope that this approach will enable the production of very small, sub-20 nm features, with low defect densities, with very smooth topologies (ie, with low line edge roughnesses).

自组装纳米结构仍然是激烈的研究的焦点，因为它们明显的灵感来自自然，其次，它们在几乎没有外部干预的情况下图案化纳米结构的巨大效用。挑战在于以经济可行的方式制造大面积的高密度金属和分子纳米结构，其特征尺寸低于20 nm，用于广泛的应用。虽然光刻技术将可持续地保持为计算机工业中即将到来的22 nm一代的核心技术，但是大规模制造的成本考虑，特别是关于光刻的成本考虑，仍然是亚22 nm时代的主要限制。因此，人们对开发涉及大规模自组装的互补图案化策略非常感兴趣，其中软有机模板进行“艰苦工作”，以快速和可预测的方式自发形成纳米级组件。在这个拟议的计划中，我们将概述我们的方法对使用自组装嵌段共聚物（BCP）纳米结构的技术相关的半导体材料，以产生子20纳米的功能。国际半导体路线图（ITRS，www.itrs.net，新兴研究材料章节）将BCP称为在某些光刻应用中应用的可能的“创新技术”，但仍存在许多挑战。例如，大多数嵌段共聚物特征的自然（或原生）间距大于10 nm，因为较小的聚合物分子量可能不会相分离，并且在其他情况下，嵌段共聚物自组装太慢而不能商业使用。为了改善这两个约束，以及其他与BCP自组装中错误率最小化相关的约束，我们将进行两个主要项目，如下所述。该计划的第一个项目将解决BCP自组装在半导体行业中应用所面临的主要挑战之一，以及更广泛的其他应用，包括生物医学问题。正如国际半导体路线图所述，实现商业化需要更快的退火和自组装;在ITRS的最新版本（2011年）中，我们使用微波退火的工作被引用为解决这一问题的可能途径。然而，到目前为止，从基本的角度以及在硅（或其他材料）制造工艺内的集成的背景下，几乎没有理解。我们建议通过详细的原位研究来解决与微波工艺相关的非常浅的理解，将微波的使用扩展到使BCP退火能够在微波照射后不加热的材料，并引入一种新的有用的手段来图案化BCP组件，其使用微波敏感模板，这将引起非常局部的加热，因此退火。该计划的第二个项目侧重于大幅度降低BCP组件的缺陷密度，ITRS的目标是每0.01 cm 2小于一个缺陷，同时将特征间距降低到10 nm以下。为了实现这些目标，我们建议使用我们最近发表的密度加倍方法，与BCP的混合物。密度加倍将自组装嵌段共聚物特征的自然间距或节距减小两倍。使用我们的内部算法来计算缺陷密度，我们将快速筛选这些密度加倍的BCP混合物，识别关键引线，并优化这些引线。我们希望这种方法能够生产出非常小的亚20 nm特征，具有低缺陷密度，具有非常光滑的拓扑结构（即具有低线边缘粗糙度）。