Fundamentals and Applications of Self-Assembly of Block Copolymer Nanostructures on Surfaces

自组装纳米结构一直是激烈研究的焦点，因为它们明显来自大自然的灵感，其次，它们在几乎没有外界干预的情况下对纳米级结构进行图图化的巨大效用。挑战在于如何以经济可行的方式制造大面积高密度金属和分子纳米结构，其特征尺寸小于20nm，以实现广泛的应用。虽然光刻技术仍将是即将到来的22纳米一代计算机行业的核心技术，但大规模生产的成本考虑，特别是光刻技术，仍然是亚22纳米时代的主要制约因素。因此，人们对开发涉及大规模自组装的互补模式策略非常感兴趣，在这种策略中，软有机模板执行“艰苦的工作”，以快速和可预测的方式自发形成纳米级组件。在这个拟议的计划中，我们将概述我们在技术相关的半导体材料上使用自组装嵌段共聚物（BCP）纳米结构的方法，以产生低于20纳米的特征。国际半导体路线图（ITRS, www.itrs.net，新兴研究材料章节）将bcp作为一种可能的“创新技术”应用于一些光刻应用，但仍存在许多挑战。例如，大多数BCP特征的自然（或原生）间距大于10纳米，因为较小的聚合物分子量可能无法相分离，并且在其他情况下，BCP自组装速度太慢，无法用于商业用途。为了改善这两个限制，以及其他与最小化BCP自组装错误率有关的限制，我们将进行如下所述的两个主要项目。*该计划的第一个项目将解决BCP自组装在半导体行业中的应用所面临的主要挑战之一，以及更广泛的其他应用，包括生物医学问题。正如国际半导体路线图所述，实现商业化需要更快的退火和自组装；在ITRS的最新版本（2011年）中，我们使用微波退火的工作被引用为解决这一问题的可能途径。然而，到目前为止，从基本的角度来看，以及在硅（或其他材料）制造过程中集成的背景下，人们知之甚少。我们建议通过详细的原位研究来解决与微波过程相关的非常肤浅的理解，扩展微波的使用，使BCP退火到在微波照射下不加热的材料，并引入一种新的有用的方法，使用微波敏感模板来设计BCP组件，这种模板将诱导非常局部的加热，从而退火。*该计划的第二个项目侧重于大幅降低BCP组件的缺陷密度，达到每0.01 cm2少于一个缺陷的ITRS目标，同时将特征间距减少到10 nm以下。为了实现这些目标，我们建议使用我们最近发表的密度加倍方法，混合bcp。密度加倍减少了自组装BCP特征的自然间距或间距两倍。使用我们的内部算法来计算缺陷密度，我们将快速筛选这些密度加倍的BCP混合物，确定关键线索，并优化这些线索。我们希望这种方法能够生产非常小的，低于20nm的特征，具有低缺陷密度，非常光滑的拓扑（即低线边缘粗糙度）。

Self-assembled nanostructures continue to be the focus of intense research due to their obvious inspiration from Nature, and secondly, their enormous utility for patterning nanoscale structures with little outside intervention. The challenge lies in fabricating large areas of high density metallic and molecular nanostructures, with feature sizes below 20 nm, in an economically feasible manner for a broad swath of applications. While photolithography will justifiably remain a core technology with respect to the upcoming 22 nm generation in the computer industry, cost considerations for mass manufacturing, particularly with regards to lithography, remains the primary constraint for the sub-22 nm era. As a result, there is very strong interest in the development of complementary patterning strategies that involve large scale self-assembly, in which a soft organic template carries out the "hard work", spontaneously forming nanoscale assemblies in a rapid and predictable fashion. In this proposed program, we will outline our approaches towards the use of self-assembled block copolymer (BCP) nanostructures on technologically relevant semiconductor materials, to produce sub 20-nm features. The International Roadmap for Semiconductors (ITRS, www.itrs.net, Emerging Research Materials chapter) refers to BCPs as a possible 'innovative technology' for application in some lithographic applications, but many challenges remain. For instance, the natural (or native) spacing of most BCP features is larger than 10 nm, as smaller polymer molecular weights may not phase segregate, and in other cases, BCP self-assembly is far too slow to use commercially. In order to improve both of these constraints, and others related to minimizing the error rate in BCP self-assembly, we will pursue two major projects, as described below. * The first project of this program will address the one of the major challenges facing the application of BCP self-assembly within the semiconductor industry, and more broadly for a host of other applications, including biomedical problems. As stated in the International Roadmap for Semiconductors, faster annealing and self-assembly is required to reach commercialization; in the most recent version (2011) of the ITRS, our work using microwave annealing was cited as a possible route to address this concern. As yet, however, little is understood from both a fundamental perspective, and within the context of integration within a silicon (or other material) fabrication process. We propose to address the very shallow understanding related to the microwave process through detailed in-situ studies, to extend the use of microwaves to enable BCP annealing to materials that do not heat upon microwave irradiation, and to introduce a new and useful means to pattern the BCP assemblies using microwave-sensitive templates that will induce very localized heating, and hence annealing. * The second project of the program focuses upon a dramatic reduction of the defect densities of BCP assemblies, with the stated ITRS goal of less than one defect per 0.01 cm2, while simultaneously decreasing feature spacings to below 10 nm. To accomplish these goals, we propose to use our density doubling approach recently published, with blends of BCPs. The density doubling decreases the natural spacing, or pitch, of self-assembled BCP features by a factor of two. Using our in-house algorithm to calculate defect densities, we will rapidly screen these density doubled BCP blends, identify key leads, and optimize these leads. We hope that this approach will enable the production of very small, sub-20 nm features, with low defect densities, with very smooth topologies (ie, with low line edge roughnesses).