Implementation of thin-film transistor de-multiplexer for integrated backplane drivers

用于集成背板驱动器的薄膜晶体管解复用器的实现

基本信息

  • 批准号:
    516248-2017
  • 负责人:
  • 金额:
    $ 9.11万
  • 依托单位:
  • 依托单位国家:
    加拿大
  • 项目类别:
    Idea to Innovation
  • 财政年份:
    2017
  • 资助国家:
    加拿大
  • 起止时间:
    2017-01-01 至 2018-12-31
  • 项目状态:
    已结题

项目摘要

The capability to simplify and integrate thin-film driver electronics directly onto the backplane of display and sensor array enables large-area electronics that are simpler to fabricate and provides a pathway towards mechanically flexible systems. For example, the popularity of 4K TVs and retina displays on phones and laptops require four times greater pixel density than conventional displays, increasing the demand on peripheral driver circuits. Accommodating four times as many drivers is a major challenge that 4K display manufacturers face. It is also becoming increasingly difficult to allocate space for an increasing number of connecting pads and the corresponding drivers required for each row and column in a backplane array. Similarly, for high-resolution image sensors, the need to address a high number of pixels complicates the electronic backplane design and fabrication cost for medical diagnostics. The emerging flexible electronics technology also promises mechanical flexibility at low cost but is encumbered by rigid and high-cost CMOS drivers used to address an array of pixels.The proposed project will build upon recently developed thin-film transistor logic circuitry to enhance the power, energy efficiency and reduce cost of thin-film transistor (TFTs) display backplane. The proposed implementation of de-multiplexers has the potential to reduce the number of row select pads and associated drivers by 50%, therefore significantly reducing display cost, weight while increasing energy efficiency. The carried out market research in 2016 by a third party substantiates and supports our initial assessment of the potential of the technology.
简化薄膜驱动器电子器件并将其直接集成到显示器和传感器阵列的背板上的能力使得大面积电子器件能够更简单地制造并提供通向机械柔性系统的途径。例如,手机和笔记本电脑上的4K电视和视网膜显示屏的普及需要比传统显示屏高四倍的像素密度,这增加了对外围驱动电路的需求。4倍的驱动程序是4K显示器制造商面临的主要挑战。为背板阵列中每行和列所需的越来越多的连接焊盘和相应的驱动器分配空间也变得越来越困难。类似地,对于高分辨率图像传感器,解决大量像素的需要使电子背板设计和医疗诊断的制造成本复杂化。新兴的柔性电子技术也有望以低成本实现机械灵活性,但受到用于寻址像素阵列的刚性和高成本CMOS驱动器的阻碍。拟议项目将建立在最近开发的薄膜晶体管逻辑电路的基础上,以提高功率和能源效率,并降低薄膜晶体管(TFT)显示器背板的成本。所提出的解复用器的实现方式具有将行选择焊盘和相关联的驱动器的数量减少50%的潜力,因此显著降低显示器成本、重量,同时提高能量效率。2016年由第三方进行的市场研究证实并支持了我们对该技术潜力的初步评估。

项目成果

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Sachdev, Manoj其他文献

A 6-TFT Charge-Transfer Self-Compensating Pixel Circuit for Flexible Displays
Neutron Radiation Induced Soft Error Rates for an Adjacent-ECC Protected SRAM in 28 nm CMOS
  • DOI:
    10.1109/tns.2016.2547963
  • 发表时间:
    2016-06-01
  • 期刊:
  • 影响因子:
    1.8
  • 作者:
    Neale, Adam;Sachdev, Manoj
  • 通讯作者:
    Sachdev, Manoj
A Soft Error Tolerant 10T SRAM Bit-Cell With Differential Read Capability
  • DOI:
    10.1109/tns.2009.2032090
  • 发表时间:
    2009-12-01
  • 期刊:
  • 影响因子:
    1.8
  • 作者:
    Jahinuzzaman, Shah M.;Rennie, David J.;Sachdev, Manoj
  • 通讯作者:
    Sachdev, Manoj
Body Biased Sense Amplifier With Auto-Offset Mitigation for Low-Voltage SRAMs

Sachdev, Manoj的其他文献

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{{ truncateString('Sachdev, Manoj', 18)}}的其他基金

Exploring Memory and Digital Circuit Boundaries for Energy Efficient Hardware
探索节能硬件的内存和数字电路边界
  • 批准号:
    RGPIN-2017-05044
  • 财政年份:
    2021
  • 资助金额:
    $ 9.11万
  • 项目类别:
    Discovery Grants Program - Individual
Exploring Memory and Digital Circuit Boundaries for Energy Efficient Hardware
探索节能硬件的内存和数字电路边界
  • 批准号:
    RGPIN-2017-05044
  • 财政年份:
    2020
  • 资助金额:
    $ 9.11万
  • 项目类别:
    Discovery Grants Program - Individual
Exploring Memory and Digital Circuit Boundaries for Energy Efficient Hardware
探索节能硬件的内存和数字电路边界
  • 批准号:
    DGDND-2017-00080
  • 财政年份:
    2019
  • 资助金额:
    $ 9.11万
  • 项目类别:
    DND/NSERC Discovery Grant Supplement
Exploring Memory and Digital Circuit Boundaries for Energy Efficient Hardware
探索节能硬件的内存和数字电路边界
  • 批准号:
    RGPIN-2017-05044
  • 财政年份:
    2019
  • 资助金额:
    $ 9.11万
  • 项目类别:
    Discovery Grants Program - Individual
Exploring Memory and Digital Circuit Boundaries for Energy Efficient Hardware
探索节能硬件的内存和数字电路边界
  • 批准号:
    RGPIN-2017-05044
  • 财政年份:
    2018
  • 资助金额:
    $ 9.11万
  • 项目类别:
    Discovery Grants Program - Individual
Exploring Memory and Digital Circuit Boundaries for Energy Efficient Hardware
探索节能硬件的内存和数字电路边界
  • 批准号:
    DGDND-2017-00080
  • 财政年份:
    2018
  • 资助金额:
    $ 9.11万
  • 项目类别:
    DND/NSERC Discovery Grant Supplement
Exploring Memory and Digital Circuit Boundaries for Energy Efficient Hardware
探索节能硬件的内存和数字电路边界
  • 批准号:
    RGPIN-2017-05044
  • 财政年份:
    2017
  • 资助金额:
    $ 9.11万
  • 项目类别:
    Discovery Grants Program - Individual
Exploring Memory and Digital Circuit Boundaries for Energy Efficient Hardware
探索节能硬件的内存和数字电路边界
  • 批准号:
    DGDND-2017-00080
  • 财政年份:
    2017
  • 资助金额:
    $ 9.11万
  • 项目类别:
    DND/NSERC Discovery Grant Supplement
Digital and Memory Circuits in nano-scale CMOS Technologies
纳米级 CMOS 技术中的数字和存储电路
  • 批准号:
    205034-2012
  • 财政年份:
    2016
  • 资助金额:
    $ 9.11万
  • 项目类别:
    Discovery Grants Program - Individual
Low-power logic gates in thin film technologies
薄膜技术中的低功耗逻辑门
  • 批准号:
    500171-2016
  • 财政年份:
    2016
  • 资助金额:
    $ 9.11万
  • 项目类别:
    Idea to Innovation

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