Exploring Memory and Digital Circuit Boundaries for Energy Efficient Hardware

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Impact of transistor scaling are evident everywhere. Often small as possible transistors are used to reduce the power, energy consumption, and to increase the packing density. Transistors with smaller dimensions exhibit a higher susceptibility to process variation. As a result, realization of robust, reliable circuit design becomes a challenge. In particular, SRAM circuits, and low-power, low-voltage digital circuits show higher degree of variation owing to smallest possible transistor dimensions, and low-supply voltage requirements. In this research, we will investigate variability-aware design of digital and SRAM circuits in power and voltage constrained environments. In microprocessors up to 70-80% of transistors are in SRAMs. As a consequence, various aspects of Systems on Chip (SoC) – power, energy, yield, quality, and reliability are influenced by SRAMs.