Exploring Memory and Digital Circuit Boundaries for Energy Efficient Hardware

探索节能硬件的内存和数字电路边界

• 批准号: RGPIN-2017-05044
• 负责人: Sachdev, Manoj
• 金额: $ 3.42万
• 依托单位: University of Waterloo
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2017
• 资助国家: 加拿大
• 起止时间: 2017-01-01 至 2018-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=637188
• 关键词: Exploring; Memory; Digital; Circuit; Boundaries

Impact of transistor scaling are evident everywhere. Often small as possible transistors are used to reduce the power, energy consumption, and to increase the packing density. Transistors with smaller dimensions exhibit a higher susceptibility to process variation. As a result, realization of robust, reliable circuit design becomes a challenge. In particular, SRAM circuits, and low-power, low-voltage digital circuits show higher degree of variation owing to smallest possible transistor dimensions, and low-supply voltage requirements. In this research, we will investigate variability-aware design of digital and SRAM circuits in power and voltage constrained environments. In microprocessors up to 70-80% of transistors are in SRAMs. As a consequence, various aspects of Systems on Chip (SoC) – power, energy, yield, quality, and reliability are influenced by SRAMs.

晶体管缩放的影响随处可见。通常使用尽可能小的晶体管来降低功率、能耗和增加封装密度。尺寸较小的晶体管对工艺变化的敏感性更高。因此，实现鲁棒、可靠的电路设计成为一个挑战。特别是，SRAM电路和低功率、低电压数字电路由于尽可能小的晶体管尺寸和低电源电压要求而表现出更高程度的变化。在本研究中，我们将研究功率和电压受限环境下数字和SRAM电路的可变感知设计。在微处理器中，高达70-80%的晶体管都在ram中。因此，片上系统（SoC）的各个方面——功率、能量、产量、质量和可靠性都受到sram的影响。