Exploring Memory and Digital Circuit Boundaries for Energy Efficient Hardware

晶体管缩放的影响随处可见。通常，尽可能小的晶体管用于降低功率、能量消耗和增加封装密度。 具有较小尺寸的晶体管表现出对工艺变化的较高敏感性。因此，实现鲁棒、可靠的电路设计成为一个挑战。特别地，SRAM电路和低功率、低电压数字电路由于最小可能的晶体管尺寸和低电源电压要求而显示出更高程度的变化。在本研究中，我们将探讨在功率和电压受限的环境中，数位和静态随机存取记忆体电路的可变性感知设计。在微处理器中，高达70-80%的晶体管都在SRAM中。因此，片上系统（SoC）的各个方面-功率，能量，产量，质量和可靠性都受到SRAM的影响。这项研究计划有两个主要组成部分-（i）SRAM，和（ii）逻辑电路。SRAM的主要研究目标是：（a）通过架构、电路创新降低SRAM功耗，实现可靠的超低压SRAM。具体地，设计电路技术以减轻工艺变化对重要SRAM块（诸如感测放大器、SRAM单元）的影响，以及（B）通过设计和有效实现的纠错码（ECC）来减轻软错误和弱故障的影响，这可以进一步改善低电压SRAM操作。逻辑电路的关键研究目标是超低电压、高能效的逻辑家族和实现超低电压的数字积木。本研究的长期（5年）目标是将所有这些想法放在硅中，以（a）采用28 nm CMOS技术制造全功能超低压低功耗SRAM;（B）设计和制造软错误鲁棒低功耗SRAM;（c）设计和制造低功耗低电压数字电路，例如能够在100 mV下工作的32/64 B加法器。在所有情况下，将制造测试芯片，并进行测量。**

Impact of transistor scaling are evident everywhere. Often small as possible transistors are used to reduce the power, energy consumption, and to increase the packing density. Transistors with smaller dimensions exhibit a higher susceptibility to process variation. As a result, realization of robust, reliable circuit design becomes a challenge. In particular, SRAM circuits, and low-power, low-voltage digital circuits show higher degree of variation owing to smallest possible transistor dimensions, and low-supply voltage requirements. In this research, we will investigate variability-aware design of digital and SRAM circuits in power and voltage constrained environments. In microprocessors up to 70-80% of transistors are in SRAMs. As a consequence, various aspects of Systems on Chip (SoC) – power, energy, yield, quality, and reliability are influenced by SRAMs.***This research proposal has two major components – (i) SRAMs, and (ii) Logic circuits. Key research objectives for the SRAM are: (a) lower SRAM power consumption with architectural, circuit innovation to realize a reliable, ultra-low-voltage SRAMs. In particular, devise circuit techniques to alleviate the impact of process variations on important SRAM blocks such as sense amplifiers, SRAM cells, and (b) mitigate the impact of soft errors and weak failures through hardened by design and efficient implementation Error Correcting Codes (ECC) which may further improve low-voltage SRAM operation. The key research objective for logic circuits is ultra-low-voltage, energy efficient logic family and to realize ultra-low-voltage digital building blocks. The long term (5 years) objective of this research is to put all these ideas together in silicon to (a) fabricate fully functional ultra-low-voltage; low-power SRAMs in 28 nm CMOS technology; (b) design and fabricate soft error robust low-power SRAMs; (c) design and fabricate a low-power, low-voltage digital circuits such as 32/64b adder capable of working at 100 mV. In all instances, test chips will be manufactured, and measurements will be carried out.**