A Smart and Efficient CAD Framework for Mapping Algorithms on Field Programmable Gate Arrays

用于现场可编程门阵列映射算法的智能高效 CAD 框架

• 批准号: RGPIN-2017-04016
• 负责人: Areibi, Shawki
• 金额: $ 2.04万
• 依托单位: University of Guelph
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2017
• 资助国家: 加拿大
• 起止时间: 2017-01-01 至 2018-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=637425
• 关键词: Smart; Efficient; CAD; Framework; Mapping

Accelerating high-performance computing (HPC) applications with Field Programmable Gate Arrays (FPGAs) can potentially deliver enormous performance compared to the fixed hardware architecture of the CPU and GPU. However, many challenges and obstacles face designers today when using FPGAs. This includes the long compile time, solution quality achieved, and the problem of fitting a design onto an FPGA architecture. Accordingly, we propose to

与CPU和GPU的固定硬件架构相比，使用现场可编程门阵列（FPGA）加速高性能计算（HPC）应用程序可能会提供巨大的性能。然而，当今设计人员在使用FPGA时面临许多挑战和障碍。这包括长编译时间、解决方案质量以及将设计适配到FPGA架构上的问题。因此，我们建议