Hardware Implementation of Cryptographic Algorithms on FPGAs and ASICs

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In recent times the ability to securely store and transfer critical data and sensitive information has proved acritical factor in success of business. In this age of universal electronic connectivity, of hackers, Trojans,viruses and electronic fraud, there is an important need for security and encryption.The most widely used symmetric encryption algorithms are 3DES, RC4, Twofish and AES.Examples of algorithms used in Asymmetric encryption are RSA, XTR and Diffie-Hellman.All the above mentioned algorithms can be implemented in either software or hardware. Hardware accelerationis the use of hardware to perform a task more efficiently than is possible in software. In order to achieve higherperformance in today's heavily loaded communication networks, utilization of hardware accelerators forcryptography algorithms is more efficient. These hardware accelerators tend to offload the most computingintensive operations of encryption algorithms from the main processor.Reconfigurable logic allows the definition of new functions to be defined in hardware units, combininghardware speed and efficiency, with ability to adapt and cope in a cost effective way with expandingfunctionality, changing environmental requirements, improvements in system features, changing protocols anddata-coding standards.This proposal will perform architecture exploration to find efficient architectures for encryption algorithms.During the exploration phase, several architectures will be generated and evaluated to estimate the conflictingconstraints and objectives such as area, performance, power consumption and flexibility.