A Smart and Efficient CAD Framework for Mapping Algorithms on Field Programmable Gate Arrays

点击翻译按钮获取中文摘要

Accelerating high-performance computing (HPC) applications with Field Programmable Gate Arrays (FPGAs) can potentially deliver enormous performance compared to the fixed hardware architecture of the CPU and GPU. However, many challenges and obstacles face designers today when using FPGAs. This includes the long compile time, solution quality achieved, and the problem of fitting a design onto an FPGA architecture. Accordingly, we propose to develop a smart framework that can address the problems outlined above. First, we propose to develop an effective algorithmic solution in the form of a modular multi-level adaptive congested/timing driven analytic FPGA placement tool that is capable of producing high quality results while reducing the user experience wait-time for large scale complex applications. Second, we propose a novel machine-learning based classification system for efficiently selecting (predicting) the most appropriate flow a priori for placing/routing a new circuit, based solely on features of the circuit described at the level of a net-list in addition to the FPGA architecture. The proposed system contains a training and testing stage. The training stage involves creating a trained supervised classification model for predicting several important parameters and also the best placement/routing flows for a new circuit. Given a new circuit to place, the testing (deployment) stage uses the trained classifier model to predict the most appropriate flow to use (based on the objective(s) to be optimized) and run the placement/routing flow on the circuit; and add the circuit to the training stage's database of known circuits, enabling the framework's performance to further improve as it gains experience. Beside improving the solution quality, we also plan to reduce the compile time of the CAD flow proposed by investigating techniques for reducing runtimes through investigating efficient algorithms that measure circuit similarity and also exploitation of the low synchronization overheads in GPUs. Finally, we seek to build upon our previous work that proposed a Reconfigurable Real Time Operating System (RRTOS) for FPGAs by enhancing it with hardware accelerators that should improve scheduling and allocation of tasks. The RRTOS will aid the designer from the early design stages all the way to the actual hardware implementation.***The novelty and expected significance of the proposed framework:***- The proposed machine learning framework for algorithm selection and parameter tuning will significantly improve the quality of solutions produced and at the same time***reduce the CPU time thus enhancing the compile time of reconfigurable systems.***- The overall significance of this work will be to provide Canadian industry with scalable, smart FPGA placement and routing tools that can produce high-quality solutions, while avoiding excessively long compile times.