A Smart and Efficient CAD Framework for Mapping Algorithms on Field Programmable Gate Arrays

与CPU和GPU的固定硬件架构相比，使用现场可编程门阵列（fpga）加速高性能计算（HPC）应用程序可以提供巨大的性能。然而，设计人员在使用fpga时面临许多挑战和障碍。这包括较长的编译时间、实现的解决方案质量以及将设计拟合到FPGA架构上的问题。因此，我们建议开发一个智能框架来解决上述问题。首先，我们建议以模块化多级自适应拥塞/时序驱动的分析FPGA放置工具的形式开发一种有效的算法解决方案，该工具能够产生高质量的结果，同时减少大规模复杂应用的用户体验等待时间。其次，我们提出了一种新的基于机器学习的分类系统，用于有效地选择（预测）最适合放置/路由新电路的先验流，除了FPGA架构之外，还仅基于在网络列表级别描述的电路特征。该系统包含一个训练和测试阶段。训练阶段包括创建一个经过训练的监督分类模型，用于预测几个重要参数以及新电路的最佳布局/路由流。给定要放置的新电路，测试（部署）阶段使用经过训练的分类器模型来预测要使用的最合适的流（基于要优化的目标），并在电路上运行放置/路由流；并将该电路添加到训练阶段的已知电路数据库中，使框架的性能随着经验的积累而进一步提高。除了提高解决方案的质量外，我们还计划通过研究测量电路相似性的有效算法以及利用gpu中的低同步开销来研究减少运行时间的技术，从而减少所提出的CAD流程的编译时间。最后，我们试图建立在我们之前的工作，提出了一个可重构的实时操作系统（RRTOS）的fpga通过硬件加速器增强它，应该改善调度和任务分配。RRTOS将帮助设计人员从早期设计阶段一直到实际的硬件实现。

Accelerating high-performance computing (HPC) applications with Field Programmable Gate Arrays (FPGAs) can potentially deliver enormous performance compared to the fixed hardware architecture of the CPU and GPU. However, many challenges and obstacles face designers today when using FPGAs. This includes the long compile time, solution quality achieved, and the problem of fitting a design onto an FPGA architecture. Accordingly, we propose to develop a smart framework that can address the problems outlined above. First, we propose to develop an effective algorithmic solution in the form of a modular multi-level adaptive congested/timing driven analytic FPGA placement tool that is capable of producing high quality results while reducing the user experience wait-time for large scale complex applications. Second, we propose a novel machine-learning based classification system for efficiently selecting (predicting) the most appropriate flow a priori for placing/routing a new circuit, based solely on features of the circuit described at the level of a net-list in addition to the FPGA architecture. The proposed system contains a training and testing stage. The training stage involves creating a trained supervised classification model for predicting several important parameters and also the best placement/routing flows for a new circuit. Given a new circuit to place, the testing (deployment) stage uses the trained classifier model to predict the most appropriate flow to use (based on the objective(s) to be optimized) and run the placement/routing flow on the circuit; and add the circuit to the training stage's database of known circuits, enabling the framework's performance to further improve as it gains experience. Beside improving the solution quality, we also plan to reduce the compile time of the CAD flow proposed by investigating techniques for reducing runtimes through investigating efficient algorithms that measure circuit similarity and also exploitation of the low synchronization overheads in GPUs. Finally, we seek to build upon our previous work that proposed a Reconfigurable Real Time Operating System (RRTOS) for FPGAs by enhancing it with hardware accelerators that should improve scheduling and allocation of tasks. The RRTOS will aid the designer from the early design stages all the way to the actual hardware implementation. The novelty and expected significance of the proposed framework: - The proposed machine learning framework for algorithm selection and parameter tuning will significantly improve the quality of solutions produced and at the same time reduce the CPU time thus enhancing the compile time of reconfigurable systems. - The overall significance of this work will be to provide Canadian industry with scalable, smart FPGA placement and routing tools that can produce high-quality solutions, while avoiding excessively long compile times.