A Smart and Efficient CAD Framework for Mapping Algorithms on Field Programmable Gate Arrays

与CPU和GPU的固定硬件架构相比，使用现场可编程门阵列(FGA)加速高性能计算(HPC)应用程序可能会带来巨大的性能。然而，当今设计者在使用现场可编程门阵列时面临着许多挑战和障碍。这包括较长的编译时间、达到的解决方案质量，以及将设计适应到FPGA体系结构上的问题。因此，我们建议开发一个能够解决上述问题的智能框架。首先，我们建议开发一种有效的算法解决方案，其形式为模块化的多级自适应拥塞/时序驱动的分析型FPGA布局工具，该工具能够产生高质量的结果，同时减少大规模复杂应用的用户体验等待时间。其次，我们提出了一种新的基于机器学习的分类系统，该系统仅根据在网表级别描述的电路的特征以及FPGA体系结构来有效地选择(预测)用于布局/布线新电路的先验最合适的流。拟议的系统包括培训和测试阶段。训练阶段包括创建训练的监督分类模型，用于预测几个重要参数以及新电路的最佳布局/布线流。在给定要放置的新电路的情况下，测试(部署)阶段使用经过训练的分类器模型来预测要使用的最合适的流(基于要优化的目标(S))，并在该电路上运行布局/布线流；并且将该电路添加到训练阶段的已知电路的数据库中，从而使框架的性能随着经验的积累而进一步提高。除了提高解的质量外，我们还计划通过研究有效的电路相似性度量算法和利用GPU中的低同步开销来减少运行时间，从而减少CAD流程的编译时间。最后，我们试图在之前工作的基础上，提出了一种适用于现场可编程门阵列的可重构实时操作系统(RRTOS)，通过使用硬件加速器来增强它，从而改进任务的调度和分配。RRTOS将帮助设计人员从早期设计阶段一直到实际硬件实现。 拟议框架的新颖性和预期意义： -拟议的用于算法选择和参数调整的机器学习框架将显著提高所产生的解决方案的质量，同时 减少了CPU时间，提高了可重构系统的编译时间。 -这项工作的总体意义将是为加拿大工业提供可扩展的、智能的FPGA布局和布线工具，这些工具可以产生高质量的解决方案，同时避免过长的编译时间。

Accelerating high-performance computing (HPC) applications with Field Programmable Gate Arrays (FPGAs) can potentially deliver enormous performance compared to the fixed hardware architecture of the CPU and GPU. However, many challenges and obstacles face designers today when using FPGAs. This includes the long compile time, solution quality achieved, and the problem of fitting a design onto an FPGA architecture. Accordingly, we propose to develop a smart framework that can address the problems outlined above. First, we propose to develop an effective algorithmic solution in the form of a modular multi-level adaptive congested/timing driven analytic FPGA placement tool that is capable of producing high quality results while reducing the user experience wait-time for large scale complex applications. Second, we propose a novel machine-learning based classification system for efficiently selecting (predicting) the most appropriate flow a priori for placing/routing a new circuit, based solely on features of the circuit described at the level of a net-list in addition to the FPGA architecture. The proposed system contains a training and testing stage. The training stage involves creating a trained supervised classification model for predicting several important parameters and also the best placement/routing flows for a new circuit. Given a new circuit to place, the testing (deployment) stage uses the trained classifier model to predict the most appropriate flow to use (based on the objective(s) to be optimized) and run the placement/routing flow on the circuit; and add the circuit to the training stage's database of known circuits, enabling the framework's performance to further improve as it gains experience. Beside improving the solution quality, we also plan to reduce the compile time of the CAD flow proposed by investigating techniques for reducing runtimes through investigating efficient algorithms that measure circuit similarity and also exploitation of the low synchronization overheads in GPUs. Finally, we seek to build upon our previous work that proposed a Reconfigurable Real Time Operating System (RRTOS) for FPGAs by enhancing it with hardware accelerators that should improve scheduling and allocation of tasks. The RRTOS will aid the designer from the early design stages all the way to the actual hardware implementation. The novelty and expected significance of the proposed framework: - The proposed machine learning framework for algorithm selection and parameter tuning will significantly improve the quality of solutions produced and at the same time reduce the CPU time thus enhancing the compile time of reconfigurable systems. - The overall significance of this work will be to provide Canadian industry with scalable, smart FPGA placement and routing tools that can produce high-quality solutions, while avoiding excessively long compile times.