Design Exploration of Hardware Accelerators for Video Compression Algorithms

视频压缩算法硬件加速器的设计探索

• 批准号: 467695-2014
• 负责人: Areibi, Shawki
• 金额: $ 1.82万
• 依托单位: University of Guelph
• 依托单位国家: 加拿大
• 项目类别: Engage Grants Program
• 财政年份: 2014
• 资助国家: 加拿大
• 起止时间: 2014-01-01 至 2015-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=562228
• 关键词: Design; Exploration; Hardware; Accelerators; Video

HEVC video encoding is the latest technology that has been developed by the Joint Collaborative Team on Video Coding. HEVC provides solutions to the growing need for higher compression of moving pictures for various applications such as Internet streaming, videoconferencing, communication television broadcasting, and enabling high-end applications such as 4k video broadcasting. HEVC requires high performance solutions in the form of ASIC since general purpose processors are unable to provide the processing speed nor performance required. However, ASICs are time consuming and expensive to develop. Once the ASIC is constructed the algorithm is effectvely `frozen' in hardware, making even the smallest modification extremely costly and challenging. Furthermore, because the ASIC design cycle is so long, and standards for video encoding and compression are changing so rapidly, the ASIC is always `behind the curve'. Often an ASIC-based product is not only obsolete by the time the consumer purchases it, but it may also be obsolete by the time the design is approved. Reconfigurable computing (RC) is becoming increasingly popular as it bears the promise of combining the flexibility of software with the performance of hardware. Reconfigurable devices can serve as runtime re-usable devices for performance critical systems, which allows the reduction of the hardware resources required. Reconfigurable logic allows the definition of new functions to be defined in hardware units, combining hardware speed and efficiency, with ability to adapt and cope in a cost effective way with expanding functionality, changing environmental requirements, improvements in system features, changing protocols and data-coding standards. This proposal will perform architecture exploration to find a near optimal solution for HEVC video encoding. During the exploration phase, several architectures will be generated and evaluated to estimate the conflicting constraints and objectives such as area, performance, power consumption and flexibility. The best architecture will be eventually mapped onto an FPGA and utilized in current Magnum products.

HEVC视频编码是视频编码联合协作团队开发的最新技术。HEVC为各种应用(如互联网流媒体、视频会议、通信电视广播和支持4k视频广播等高端应用)日益增长的运动图像更高压缩需求提供解决方案。HEVC需要ASIC形式的高性能解决方案，因为通用处理器无法提供所需的处理速度和性能。然而，ASIC的开发既耗时又昂贵。一旦构建了ASIC，算法就被有效地冻结在硬件中，使得即使是最小的修改也极其昂贵和具有挑战性。此外，由于ASIC的设计周期如此之长，而视频编码和压缩标准的变化又如此之快，因此ASIC总是“落后于曲线”。通常，基于ASIC的产品不仅在消费者购买时已经过时，而且在设计获得批准时也可能已经过时。可重构计算(RC)正变得越来越流行，因为它承诺将软件的灵活性与硬件的性能相结合。可重构设备可以作为性能关键型系统的运行时可复用设备，从而减少所需的硬件资源。可重新配置逻辑允许在硬件单元中定义新功能，将硬件速度和效率结合在一起，能够以具有成本效益的方式适应和应对扩展功能、不断变化的环境要求、系统功能的改进、不断变化的协议和数据编码标准。该方案将进行架构探索，以找到HEVC视频编码的近乎最佳的解决方案。在探索阶段，将生成并评估几个体系结构，以估计相互冲突的约束和目标，如面积、性能、功耗和灵活性。最好的架构最终将被映射到一个FPGA上，并在目前的Magnum产品中使用。