Design Exploration of Hardware Accelerators for Video Compression Algorithms

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HEVC video encoding is the latest technology that has been developed by the Joint Collaborative Team on Video Coding. HEVC provides solutions to the growing need for higher compression of moving pictures for various applications such as Internet streaming, videoconferencing, communication television broadcasting, and enabling high-end applications such as 4k video broadcasting. HEVC requires high performance solutions in the form of ASIC since general purpose processors are unable to provide the processing speed nor performance required. However, ASICs are time consuming and expensive to develop. Once the ASIC is constructed the algorithm is effectvely `frozen' in hardware, making even the smallest modification extremely costly and challenging. Furthermore, because the ASIC design cycle is so long, and standards for video encoding and compression are changing so rapidly, the ASIC is always `behind the curve'. Often an ASIC-based product is not only obsolete by the time the consumer purchases it, but it may also be obsolete by the time the design is approved. Reconfigurable computing (RC) is becoming increasingly popular as it bears the promise of combining the flexibility of software with the performance of hardware. Reconfigurable devices can serve as runtime re-usable devices for performance critical systems, which allows the reduction of the hardware resources required. Reconfigurable logic allows the definition of new functions to be defined in hardware units, combining hardware speed and efficiency, with ability to adapt and cope in a cost effective way with expanding functionality, changing environmental requirements, improvements in system features, changing protocols and data-coding standards. This proposal will perform architecture exploration to find a near optimal solution for HEVC video encoding. During the exploration phase, several architectures will be generated and evaluated to estimate the conflicting constraints and objectives such as area, performance, power consumption and flexibility. The best architecture will be eventually mapped onto an FPGA and utilized in current Magnum products.