Design Exploration of Hardware Accelerators for Video Compression Algorithms

HEVC视频编码是由视频编码联合协作小组开发的最新技术。HEVC为各种应用（如互联网流媒体、视频会议、通信电视广播以及4k视频广播等高端应用）日益增长的对运动图像更高压缩的需求提供了解决方案。HEVC需要ASIC形式的高性能解决方案，因为通用处理器无法提供所需的处理速度和性能。然而，asic的开发既耗时又昂贵。一旦ASIC构建完成，算法就被有效地“冻结”在硬件中，这使得即使是最小的修改也非常昂贵和具有挑战性。此外，由于ASIC设计周期太长，视频编码和压缩标准变化太快，ASIC总是“落后于潮流”。通常，基于asic的产品不仅在消费者购买时已经过时，而且在设计被批准时也可能已经过时。可重构计算（Reconfigurable computing， RC）正变得越来越流行，因为它承诺将软件的灵活性与硬件的性能相结合。可重构设备可以作为性能关键型系统的运行时可重用设备，从而减少所需的硬件资源。可重构逻辑允许在硬件单元中定义新功能，结合硬件速度和效率，能够以经济有效的方式适应和应对扩展功能，改变环境要求，改进系统功能，改变协议和数据编码标准。本提案将进行架构探索，以找到HEVC视频编码的接近最佳解决方案。在探索阶段，将生成和评估几个架构，以评估冲突的约束和目标，如面积、性能、功耗和灵活性。最好的架构最终将映射到FPGA上，并用于当前的Magnum产品。

HEVC video encoding is the latest technology that has been developed by the Joint Collaborative Team on Video Coding. HEVC provides solutions to the growing need for higher compression of moving pictures for various applications such as Internet streaming, videoconferencing, communication television broadcasting, and enabling high-end applications such as 4k video broadcasting. HEVC requires high performance solutions in the form of ASIC since general purpose processors are unable to provide the processing speed nor performance required. However, ASICs are time consuming and expensive to develop. Once the ASIC is constructed the algorithm is effectvely `frozen' in hardware, making even the smallest modification extremely costly and challenging. Furthermore, because the ASIC design cycle is so long, and standards for video encoding and compression are changing so rapidly, the ASIC is always `behind the curve'. Often an ASIC-based product is not only obsolete by the time the consumer purchases it, but it may also be obsolete by the time the design is approved. Reconfigurable computing (RC) is becoming increasingly popular as it bears the promise of combining the flexibility of software with the performance of hardware. Reconfigurable devices can serve as runtime re-usable devices for performance critical systems, which allows the reduction of the hardware resources required. Reconfigurable logic allows the definition of new functions to be defined in hardware units, combining hardware speed and efficiency, with ability to adapt and cope in a cost effective way with expanding functionality, changing environmental requirements, improvements in system features, changing protocols and data-coding standards. This proposal will perform architecture exploration to find a near optimal solution for HEVC video encoding. During the exploration phase, several architectures will be generated and evaluated to estimate the conflicting constraints and objectives such as area, performance, power consumption and flexibility. The best architecture will be eventually mapped onto an FPGA and utilized in current Magnum products.