A unified congestion driven power aware methodology for VLSI physical design automation

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The layout of integrated circuits on chips and boards (physical design) is one of many interrelated complex tasks in VLSI circuit design. A major portion of the research in the area of design automation has been devoted to the development of efficient and easy-to-use systems that support circuit layout. Today's embedded systems contain various combinations of different components in the form of microprocessors, memories and application specific integrated circuits (ASICS). All this cannot be achieved without advanced and suitable CAD tools including physical design automation. The interconnect delay in VLSI circuits has become a critical determiner of circuit performance. It seems to become more and more important to know the impact of interconnection on speed and power consumption early in the design trajectory of high-performance processors and Systems-on-Chip. As a  result, circuit layout is starting to play a more important role in today's chip designs.Advances in process technology are driving the convergence of communication, computing, and sensor technologies onto a single silicon substrate -- Systems on a Chip (SoC). SoC will change the way future civilian/military systems are conceptualized and designed. Opportunities created by this development for electronic companies are clear, but with these possibilities also come significant design issues that have to be addressed and grand challenges that must be solved. The proposed approach seeks to achieve the following milestones: (i) integrate mathematical based methods with advanced meta-heuristics to solve the underlying hard optimization problems in circuit layout for Systems-on-Chip effectively and efficiently, (ii) reduce thetremendous complexity associated with System-on-Chip design by utilizing hierarchical/multilevel optimization approaches, (iii) tackle the low power design problem by considering it early and within physical design sub-problems, (iv) speedup the algorithms developed using special hardware accelerators for partitioning, placement and routing.