Further Development and Evaluation of an Automated Image Analysis Pipeline for Semiconductor Circuit Reverse Engineering

本提案的目的是开发一种软件工具，包括一套图像分析技术，以帮助自动检测与集成电路（IC）中的电路相关的专利侵权。我们提出的软件将有助于自动化的过程中，电路提取，其中一个集成电路是逆向工程，以确定其电子电路的确切结构和设计。电路提取有时需要确定专利侵权。电路提取的过程是通过单独移除IC的电路层、使用扫描电子显微镜（SEM）对层进行成像以及分析IC布局的SEM图像以重建电路原理图来执行的。现有方法的主要瓶颈之一是从SEM图像中准确分割出精确的IC版图，因为分割中的微小误差通常会导致重构的IC原理图中的重大错误。基于图像强度阈值的方法，例如TechInsights目前用于分割SEM图像的方法，在图像噪声下往往表现不佳，需要繁琐的人工检查和校正，因此增加了生产成本。在之前的NSERC Engage项目中，我们开发了一个图像分析管道，它包括一个图像归一化方法，两个图像滤波器和两个图像分割方法，用于导线和垂直互连通路（VIA）。初步结果表明，与TechInsights目前使用的方法相比，使用开发的管道获得的分割结果提供了更准确的IC布局分割。在这个提议的NSERC Engage Plus项目中，我们将扩展最近开发的管道来解决以下剩余的挑战：1）不仅利用使用背散射电子创建的SEM图像，而且还利用使用二次电子创建的SEM图像; 2）由于图像伪影，需要两种单独的算法来分割导线和VIA导致较差的结果; 3）为给定的SEM图像数据集选择优化的参数; 4）水平集分割方法计算时间长。我们将开发一种多区域分割方法

The objective of this proposal is to develop a software tool consisting of a suite of image analysis techniques tohelp automate the detection of patents infringement related to circuitry in integrated circuits (ICs). Ourproposed software will aid in automating the process of circuit extraction, where an IC is reverse engineered todetermine the exact construction and design of its electronic circuitry. Circuit extraction is sometimes requiredto determine infringement of patent(s). The process of circuit extraction is performed by individually removinglayers of circuitry of an IC, imaging the layers using a scanning electron microscope (SEM), and analysingSEM images of the IC layout to reconstruct the circuit schematics. One of the main bottlenecks in the existingapproach is the accurate segmentation of the precise IC layout from SEM images, because minute errors insegmentation usually lead to significant errors in the reconstructed IC schematics. Image intensitythreshold-based methods, such as the one used currently by TechInsights to segment the SEM images tends toperform poorly under image noise, requires tedious manual inspection and correction and consequently resultsin increased production costs. In the previous NSERC Engage project, we developed an image-analysispipeline, which consisted of an image normalization method, two image filters and two image segmentationmethods for wires and vertical interconnect accesses (VIAs). The preliminary results indicated that thesegmentation results obtained using the developed pipeline, as compared to the methods currently used byTechInsights, provided more accurate segmentations of the IC layout. In this proposed NSERC Engage Plusproject, we will expand the recently developed pipeline to address the following remaining challenges: 1)utilizing not only SEM images created using backscattered electrons, but also the ones created using secondaryelectrons; 2) requiring two separate algorithms for segmenting wires and VIAs lead to inferior results due toimage artifacts; 3) choosing optimized parameters for a given SEM image dataset; and 4) the longcomputational time of the level set segmentation method. We will develop a multi-region segmentation method