Development of automated image analysis pipeline for semiconductor circuit reverse engineering

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The objective of this proposal is to develop a software tool consisting of image analysis techniques to help automate the detection of infringement of patents related to circuitry in integrated circuits (ICs). Our proposed software will aid in automating the process of circuit extraction, where an IC is reverse engineered to determine the exact construction of its electronic circuitry. Circuit extraction exposes the design of an IC, and is sometimes required in order to determine if there has been infringement of a patent. The process of circuit extraction is performed by individually removing layers of circuitry of an IC, imaging them using an electron microscope, and analysing microscopic images of the IC layout to reconstruct the circuit schematics. One of the main bottlenecks in the existing approach is the accurate segmentation of the precise IC layout, because minute errors in segmentation usually lead to significant errors in reconstructed IC schematics. Currently, TechInsights uses image intensity threshold-based methods for this segmentation, which tend to perform poorly under image noise, requiring tedious manual inspection and correction, resulting in increased production cost. In this project, we will determine the feasibility of incorporating state-of-the-art image segmentation methods to address some key technical challenges in analysis of IC layout in electron microscopic images. In conjunction with our industrial partner, TechInsights, we intend to increase the accuracy and speed of this segmentation by developing a new image segmentation method and an automated mechanism to alert the operator on errors in segmentation. In the proposed approach, as compared to threshold-based methods, boundary regularization along with image information will be incorporated into the segmentation to increase the robustness to image noise and regional variations in image intensity. A second tool would attempt to determine the validity of segmented IC layout using a library of design-specification rules. These two tools will ensure improved