The Development of Successive Approximation Register Analog-to-Digital Converter Using Time-Mode Approaches

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Analog-to-digital converters (ADCs) play a critical role in almost every aspect of our life. Various architecturesof ADCs are available. Among them, flash, delta-sigma, and successive approximation register (SAR) ADCsemerged as dominant architectures. Flash ADCs offer the highest conversion rate and are widely popular inapplications such as high-speed data communications over wire and optical channels. The exponentially risingsilicon area and power consumption with bit resolution and difficulties in combating comparator mismatchlimit their resolution to no more than 6 bits. Delta-sigma ADCs achieve the highest resolution by means ofoversampling and noise-shaping. These ADCs are effective if signal bandwidth is small. SAR ADCs,introduced in 1950s and sat its debut in CMOS in 1970s, has played a significant role in advancing thestate-of-the-art in ADCs since their inception. Although popular in telephony and low-speed instruments priorto the turning of 20th century, SAR ADCs have re-established themselves as the most promising ADCarchitecture inherently crafted for modern CMOS technologies with emerging applications ranging frombiomedical implants where power consumption is most critical to high-speed data links where conversion rateis pivotal, accredited to their compatibility with technology scaling. The key functional block of SAR ADCs isa digital-to-analog converter realized using capacitor arrays. At high conversion rates, the dynamic powerconsumption of the capacitor arrays becomes prohibitively large. The silicon area needed to realize capacitorarrays also rises exponentially with bit resolution. Recently the feasibility of deploying time-mode techniquesin SAR ADCs was explored. As compared with SAR ADCs with binary-weighted capacitor arrays, time-modeSAR ADCs offer the possibility of eliminating capacitor arrays so as to drastically lower power consumptionand silicon area. The objective of this project is to develop and prototype an 8-bit 1 GS/s SAR ADC using atime-mode approach.