The Development of Successive Approximation Register Analog-to-Digital Converter Using Time-Mode Approaches

模数转换器（adc）在我们生活的几乎每个方面都起着至关重要的作用。adc的结构多种多样。其中，flash、delta-sigma和逐次逼近寄存器（SAR） adc成为主流架构。Flash adc提供最高的转换率，在诸如通过有线和光通道的高速数据通信等应用中广泛流行。由于硅的面积和功耗呈指数级增长，分辨率和对抗比较器不匹配的困难限制了它们的分辨率不超过6位。δ - σ adc通过过采样和噪声整形实现最高分辨率。这些adc在信号带宽小的情况下是有效的。SAR adc于20世纪50年代推出，并于20世纪70年代在CMOS中首次亮相，自成立以来在推进adc的最新技术方面发挥了重要作用。虽然在20世纪之交之前在电话和低速仪器中很受欢迎，但SAR adc已经重新确立了自己作为最有前途的adc架构的地位，该架构为现代CMOS技术精心设计，具有新兴应用范围，从功耗最关键的生物医学植入物到转换率至关重要的高速数据链路，认可其与技术扩展的兼容性。SAR adc的关键功能模块是利用电容阵列实现的数模转换器。在高转换率下，电容器阵列的动态功耗变得非常大。实现电容阵列所需的硅面积也随着位分辨率呈指数级增长。近年来研究了在SAR adc中部署时模技术的可行性。与二元加权电容阵列的SAR adc相比，时模desar adc提供了消除电容阵列的可能性，从而大大降低了功耗和硅面积。该项目的目的是开发和原型一个8位1 GS/s SAR ADC使用时间模式的方法。

Analog-to-digital converters (ADCs) play a critical role in almost every aspect of our life. Various architecturesof ADCs are available. Among them, flash, delta-sigma, and successive approximation register (SAR) ADCsemerged as dominant architectures. Flash ADCs offer the highest conversion rate and are widely popular inapplications such as high-speed data communications over wire and optical channels. The exponentially risingsilicon area and power consumption with bit resolution and difficulties in combating comparator mismatchlimit their resolution to no more than 6 bits. Delta-sigma ADCs achieve the highest resolution by means ofoversampling and noise-shaping. These ADCs are effective if signal bandwidth is small. SAR ADCs,introduced in 1950s and sat its debut in CMOS in 1970s, has played a significant role in advancing thestate-of-the-art in ADCs since their inception. Although popular in telephony and low-speed instruments priorto the turning of 20th century, SAR ADCs have re-established themselves as the most promising ADCarchitecture inherently crafted for modern CMOS technologies with emerging applications ranging frombiomedical implants where power consumption is most critical to high-speed data links where conversion rateis pivotal, accredited to their compatibility with technology scaling. The key functional block of SAR ADCs isa digital-to-analog converter realized using capacitor arrays. At high conversion rates, the dynamic powerconsumption of the capacitor arrays becomes prohibitively large. The silicon area needed to realize capacitorarrays also rises exponentially with bit resolution. Recently the feasibility of deploying time-mode techniquesin SAR ADCs was explored. As compared with SAR ADCs with binary-weighted capacitor arrays, time-modeSAR ADCs offer the possibility of eliminating capacitor arrays so as to drastically lower power consumptionand silicon area. The objective of this project is to develop and prototype an 8-bit 1 GS/s SAR ADC using atime-mode approach.