Raising the Energy Efficiency of Mobile and Cloud Computing with FPGAs

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Recent years have seen dramatic growth at the extreme ends of the computing spectrum: 1) lightweight inexpensive battery-powered mobile clients (e.g. laptops, tablets, smartphones), and 2) "cloud" compute farms with thousands of server-class machines. Field-programmable gate arrays (FPGAs) are programmable chips that can be configured by the end user to implement digital circuit. As such, they are gaining traction in computing applications where they implement custom accelerators that are specially tailored to an application's needs. Naturally, the programmability of FPGAs involves an overhead and indeed, FPGAs are slower, consume more area, and are less energy efficient than a functionally-equivalent custom (i.e. non-programmable) chip. However, while FPGAs are indeed less efficient than custom chips, they can be orders of magnitude more efficient than processors for implementing computations, both from the energy and computational throughput perspectives. FPGAs are a $6 billion dollar industry, and are widely used in diverse applications, especially in communications, automotive, and industrial electronics. However, despite their speed and energy supremacy over processors, two factors have impeded a broad uptake of FPGAs for general computing: 1) their high power consumption vs. custom chips, and 2) ease-of-use: their use has required knowledge of hardware design techniques and compute-intensive CAD tools, making them an inaccessible and/or unattractive technology for software engineers. These are precisely the two obstacles addressed in the proposed research.**A first research thrust centres on low-power FPGA circuits and architecture. Interconnect is the prime culprit in FPGA power consumption. The proposed research addresses FPGA interconnect power in two ways: charge recycling, and a new signalling style: time-based signalling. Charge recycling saves energy by storing charge on unused conductors within an FPGA, instead of dumping it to ground. The charge is then recovered when used conductors need to make a rising transition. In time-based signalling, the timing of a specific event -- a transition -- is used to encode multiple bits of information. For example, one can send 4 bits of information using a transition on a wire at one of 16 possible time slots. While traditional approaches use 4 parallel wires to send 4 bits of information, a single transition at a particular time is required in the proposed style, lowering energy consumption. The proposed signalling style requires the use of digital-to-time converters (at the sender) and time-to-digital converters (at the receiver). The projects will involve circuit design, architecture, and CAD techniques to cluster drivers/receivers together physically to enable the efficient coupling of multiple bits into a single timed event.**A second research direction concerns the ease with which FPGAs may be used as computing platforms targetable by software engineers to raise computational throughput and improve energy efficiency. Over the past several years, we have been developing a high-level synthesis tool at Toronto, called LegUp, which can synthesize a software program in a standard language (C) to an FPGA hardware circuit. The project has been very successful, with over 700 downloads of the tool from around the world. What is proposed under this grant are tools and methodologies to: 1) improve the quality (i.e. speed and power consumption) of the generated hardware by automated clock gating and speculative/predicated execution of computations, and 2) ease the integration of the synthesized hardware with software running on Intel and ARM processors, as are present in cloud and mobile settings, respectively.