Software-Specified Hardware Acceleration for Energy-Efficient Computing

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Whether it be Uber ride-sharing, social media, or Netflix video streaming, data centre (cloud) computing is the "workhorse" behind countless applications we depend on in today's digital connected society. Data centres represent about 3% of the world's total energy consumption, however, a recent study predicted that they may account for an astounding ~7% of the world's electricity consumed by 2030. The majority of computational work in data centres is done by standard microprocessors. While such processors benefit from logic density increases afforded by Moore's Law, energy efficiency has not improved at the same rate. A proven approach to raise energy efficiency is to customize the computing hardware to the computing task, eliminating the overheads incurred by a generic microprocessor, such as fetching/decoding instructions. Field-programmable gate arrays (FPGAs) are programmable chips that can be configured to realize any digital circuit. FPGAs are thus an ideal media on which to implement custom compute accelerators in data centres, and have been shown to produce orders-of-magnitude improvements in energy efficiency. Major cloud-computing providers have recently announced the deployment of FPGAs in their data centres -- a "game changer" for what was once seen as a niche technology. FPGAs are now a part of the sharing economy: from anywhere in the world, one can rent a cloud FPGA for accelerated energy-efficient custom computing.    FPGAs are poised for a prominent role in energy-efficient data centre computing, however, a challenge is that they are difficult to use by software engineers for two primary reasons: 1) implementing a circuit on an FPGA has historically required knowledge of hardware design, where the circuit is described at a low level of abstraction in a hardware description language, such as VHDL or Verilog, and 2) compiling a design for an FPGA is time intensive, taking up to hours or days, preventing the real-time design -> debug -> execute iterative cycle that software engineers are accustomed to. What is needed is for FPGAs to be software programmable, with the desired behaviour specified at a high level of abstraction, and new approaches and architectures that permit such specifications to be rapidly compiled into the underlying FPGA hardware.    A first thrust undertaken to address the FPGA usability challenge is the application of machine learning techniques within high-level synthesis (HLS). HLS is the automated synthesis of a hardware circuit from a software program. Presently, the quality of circuit (power, performance, area) produced by HLS tools is inferior to human-expert designed hardware. HLS tools are by nature heuristic approaches, and we propose to apply machine learning algorithms, within HLS itself, to raise circuit quality. A second research thrust concerns the architecture of the target FPGA. We propose to attack today's lengthy compile times through compile-time-friendly architectural changes.