Raising the Energy Efficiency of Mobile and Cloud Computing with FPGAs

利用 FPGA 提高移动和云计算的能源效率

• 批准号: RGPIN-2014-04749
• 负责人: Anderson, Jason
• 金额: $ 2.26万
• 依托单位: University of Toronto
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2017
• 资助国家: 加拿大
• 起止时间: 2017-01-01 至 2018-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=637193
• 关键词: Raising; Energy; Efficiency; Mobile; Cloud

Recent years have seen dramatic growth at the extreme ends of the computing spectrum: 1) lightweight inexpensive battery-powered mobile clients (e.g. laptops, tablets, smartphones), and 2) "cloud" compute farms with thousands of server-class machines. Field-programmable gate arrays (FPGAs) are programmable chips that can be configured by the end user to implement digital circuit. As such, they are gaining traction in computing applications where they implement custom accelerators that are specially tailored to an application's needs. Naturally, the programmability of FPGAs involves an overhead and indeed, FPGAs are slower, consume more area, and are less energy efficient than a functionally-equivalent custom (i.e. non-programmable) chip. However, while FPGAs are indeed less efficient than custom chips, they can be orders of magnitude more efficient than processors for implementing computations, both from the energy and computational throughput perspectives. FPGAs are a $6 billion dollar industry, and are widely used in diverse applications, especially in communications, automotive, and industrial electronics. However, despite their speed and energy supremacy over processors, two factors have impeded a broad uptake of FPGAs for general computing: 1) their high power consumption vs. custom chips, and 2) ease-of-use: their use has required knowledge of hardware design techniques and compute-intensive CAD tools, making them an inaccessible and/or unattractive technology for software engineers. These are precisely the two obstacles addressed in the proposed research.A first research thrust centres on low-power FPGA circuits and architecture. Interconnect is the prime culprit in FPGA power consumption. The proposed research addresses FPGA interconnect power in two ways: charge recycling, and a new signalling style: time-based signalling. Charge recycling saves energy by storing charge on unused conductors within an FPGA, instead of dumping it to ground. The charge is then recovered when used conductors need to make a rising transition. In time-based signalling, the timing of a specific event -- a transition -- is used to encode multiple bits of information. For example, one can send 4 bits of information using a transition on a wire at one of 16 possible time slots. While traditional approaches use 4 parallel wires to send 4 bits of information, a single transition at a particular time is required in the proposed style, lowering energy consumption. The proposed signalling style requires the use of digital-to-time converters (at the sender) and time-to-digital converters (at the receiver). The projects will involve circuit design, architecture, and CAD techniques to cluster drivers/receivers together physically to enable the efficient coupling of multiple bits into a single timed event.A second research direction concerns the ease with which FPGAs may be used as computing platforms targetable by software engineers to raise computational throughput and improve energy efficiency. Over the past several years, we have been developing a high-level synthesis tool at Toronto, called LegUp, which can synthesize a software program in a standard language (C) to an FPGA hardware circuit. The project has been very successful, with over 700 downloads of the tool from around the world. What is proposed under this grant are tools and methodologies to: 1) improve the quality (i.e. speed and power consumption) of the generated hardware by automated clock gating and speculative/predicated execution of computations, and 2) ease the integration of the synthesized hardware with software running on Intel and ARM processors, as are present in cloud and mobile settings, respectively.

近年来，计算领域的极端领域出现了戏剧性的增长：1)重量轻、价格低廉、由电池供电的移动客户端(例如笔记本电脑、平板电脑、智能手机)，以及2)拥有数千台服务器级机器的“云”计算场。现场可编程门阵列(现场可编程门阵列)是一种可编程芯片，可由最终用户配置以实现数字电路。因此，他们在计算应用程序中获得了吸引力，他们实现了专门为应用程序需求量身定做的定制加速器。当然，FPGA的可编程性涉及开销，而且实际上，与功能等价的定制(即不可编程)芯片相比，FPGA速度更慢、消耗更多面积、能效更低。然而，尽管现场可编程门阵列的效率确实低于定制芯片，但从能量和计算吞吐量的角度来看，它们在实现计算方面的效率可以比处理器高出数量级。现场可编程门阵列是一个价值60亿美元的行业，广泛应用于各种应用，特别是在通信、汽车和工业电子领域。然而，尽管现场可编程门阵列在速度和能量方面领先于处理器，但有两个因素阻碍了它们在通用计算领域的广泛应用：1)与定制芯片相比，它们的高功耗；2)易用性：它们的使用需要硬件设计技术和计算密集型CAD工具的知识，使得它们对于软件工程师来说是一项难以获得和/或缺乏吸引力的技术。这正是拟议研究中要解决的两个障碍。第一个研究重点集中在低功耗的FPGA电路和架构上。互连是影响现场可编程门阵列功耗的元凶。这项拟议的研究通过两种方式解决了现场可编程门阵列的互连电源问题：电荷回收，以及一种新的信令方式：基于时间的信令。电荷回收通过将电荷存储在现场可编程门阵列内未使用的导线上而不是将其倾倒到地面来节省能源。然后，当用过的导体需要进行上升转变时，电荷被回收。在基于时间的信令中，特定事件--转换--的定时被用来编码多比特的信息。例如，可以在16个可能的时隙中的一个在线路上使用转换来发送4比特的信息。传统的方法使用4条平行线来发送4比特的信息，而在所提出的方式中，需要在特定时间进行一次转换，从而降低了能耗。建议的信令方式需要使用数字到时间转换器(在发送方)和时间到数字转换器(在接收方)。这些项目将涉及电路设计、体系结构和CAD技术，以将驱动器/接收器物理地聚集在一起，以使多个位能够有效地耦合到单个定时事件中。第二个研究方向涉及现场可编程门阵列作为计算平台的容易程度，软件工程师可以将其作为目标，以提高计算吞吐量和能源效率。在过去的几年里，我们一直在多伦多开发一种高级综合工具，称为LEGUP，它可以将标准语言(C)的软件程序综合到FPGA硬件电路上。该项目非常成功，从世界各地下载了700多次该工具。根据这项拨款，建议的工具和方法是：1)通过自动时钟门控和推测性/预测性计算执行来提高生成硬件的质量(即速度和功耗)，以及2)简化合成硬件与运行在英特尔和ARM处理器上的软件的集成，分别出现在云和移动环境中。