Software-Specified Hardware Acceleration for Energy-Efficient Computing

无论是优步拼车、社交媒体还是Netflix视频流媒体，数据中心（云）计算都是我们在当今数字互联社会中所依赖的无数应用背后的“主力”。数据中心约占世界总能耗的3%，然而，最近的一项研究预测，到2030年，它们可能占世界用电量的7%，这一数字令人震惊。数据中心的大部分计算工作是由标准微处理器完成的。虽然这样的处理器得益于摩尔定律所带来的逻辑密度的增加，但能源效率却没有以同样的速度提高。提高能源效率的一种经过验证的方法是根据计算任务定制计算硬件，从而消除通用微处理器带来的开销，例如获取/解码指令。现场可编程门阵列（fpga）是一种可编程芯片，可以配置成实现任何数字电路。因此，fpga是在数据中心实现定制计算加速器的理想媒介，并且已被证明可以在能源效率方面产生数量级的改进。主要的云计算提供商最近宣布在他们的数据中心部署fpga，这是曾经被视为利基技术的“游戏规则改变者”。FPGA现在是共享经济的一部分：在世界任何地方，人们都可以租用云FPGA来加速节能定制计算。

Whether it be Uber ride-sharing, social media, or Netflix video streaming, data centre (cloud) computing is the "workhorse" behind countless applications we depend on in today's digital connected society. Data centres represent about 3% of the world's total energy consumption, however, a recent study predicted that they may account for an astounding ~7% of the world's electricity consumed by 2030. The majority of computational work in data centres is done by standard microprocessors. While such processors benefit from logic density increases afforded by Moore's Law, energy efficiency has not improved at the same rate. A proven approach to raise energy efficiency is to customize the computing hardware to the computing task, eliminating the overheads incurred by a generic microprocessor, such as fetching/decoding instructions. Field-programmable gate arrays (FPGAs) are programmable chips that can be configured to realize any digital circuit. FPGAs are thus an ideal media on which to implement custom compute accelerators in data centres, and have been shown to produce orders-of-magnitude improvements in energy efficiency. Major cloud-computing providers have recently announced the deployment of FPGAs in their data centres -- a "game changer" for what was once seen as a niche technology. FPGAs are now a part of the sharing economy: from anywhere in the world, one can rent a cloud FPGA for accelerated energy-efficient custom computing. FPGAs are poised for a prominent role in energy-efficient data centre computing, however, a challenge is that they are difficult to use by software engineers for two primary reasons: 1) implementing a circuit on an FPGA has historically required knowledge of hardware design, where the circuit is described at a low level of abstraction in a hardware description language, such as VHDL or Verilog, and 2) compiling a design for an FPGA is time intensive, taking up to hours or days, preventing the real-time design -> debug -> execute iterative cycle that software engineers are accustomed to. What is needed is for FPGAs to be software programmable, with the desired behaviour specified at a high level of abstraction, and new approaches and architectures that permit such specifications to be rapidly compiled into the underlying FPGA hardware. A first thrust undertaken to address the FPGA usability challenge is the application of machine learning techniques within high-level synthesis (HLS). HLS is the automated synthesis of a hardware circuit from a software program. Presently, the quality of circuit (power, performance, area) produced by HLS tools is inferior to human-expert designed hardware. HLS tools are by nature heuristic approaches, and we propose to apply machine learning algorithms, within HLS itself, to raise circuit quality. A second research thrust concerns the architecture of the target FPGA. We propose to attack today's lengthy compile times through compile-time-friendly architectural changes.