Software-Specified Hardware Acceleration for Energy-Efficient Computing

无论是优步拼车、社交媒体，还是Netflix视频流，数据中心(云)计算都是当今数字互联社会中我们所依赖的无数应用背后的主力。数据中心约占世界总能源消耗的3%，然而，最近的一项研究预测，到2030年，它们可能占到世界电力消耗的7%左右，这一数字令人震惊。数据中心的大部分计算工作是由标准微处理器完成的。虽然这样的处理器受益于摩尔定律提供的逻辑密度增加，但能效并没有以同样的速度提高。提高能效的一种行之有效的方法是根据计算任务定制计算硬件，消除通用微处理器产生的开销，例如获取/解码指令。现场可编程门阵列(现场可编程门阵列)是可编程芯片，可以配置为实现任何数字电路。因此，现场可编程门阵列是在数据中心实施定制计算加速器的理想媒介，并已被证明能在能源效率方面产生数量级的改善。各大云计算提供商最近宣布在他们的数据中心部署现场可编程门阵列--这是一项曾经被视为利基技术的“游戏规则改变者”。现场可编程门阵列现在是共享经济的一部分：在世界任何地方，你都可以租用一台云现场可编程门阵列，用于加速节能的定制计算。 在高能效的数据中心计算中，现场可编程门阵列将扮演重要角色，然而，挑战在于，软件工程师很难使用它们，主要原因有两个：1)在现场可编程门阵列上实现电路历来需要硬件设计知识，在这种情况下，用硬件描述语言(如VHDL语言或Verilog)以较低的抽象级别描述电路；以及2)为现场可编程门阵列编译设计是时间密集型的，需要长达数小时或数天的时间，阻碍了软件工程师习惯的实时设计-调试-执行迭代周期。所需要的是使FPGA是软件可编程的，并在高抽象级别上指定所需的行为，以及允许将此类规范快速编译到底层FPGA硬件中的新方法和体系结构。 解决现场可编程门阵列可用性挑战的第一个推力是在高级综合(HLS)中应用机器学习技术。HLS是从软件程序自动综合硬件电路。目前，HLS工具生产的电路质量(功率、性能、面积)低于人类专家设计的硬件。HLS工具本质上是启发式方法，我们建议在HLS本身中应用机器学习算法来提高电路质量。第二个研究重点涉及目标现场可编程门阵列的架构。我们建议通过对编译时间友好的架构更改来解决当今漫长的编译时间问题。

Whether it be Uber ride-sharing, social media, or Netflix video streaming, data centre (cloud) computing is the "workhorse" behind countless applications we depend on in today's digital connected society. Data centres represent about 3% of the world's total energy consumption, however, a recent study predicted that they may account for an astounding ~7% of the world's electricity consumed by 2030. The majority of computational work in data centres is done by standard microprocessors. While such processors benefit from logic density increases afforded by Moore's Law, energy efficiency has not improved at the same rate. A proven approach to raise energy efficiency is to customize the computing hardware to the computing task, eliminating the overheads incurred by a generic microprocessor, such as fetching/decoding instructions. Field-programmable gate arrays (FPGAs) are programmable chips that can be configured to realize any digital circuit. FPGAs are thus an ideal media on which to implement custom compute accelerators in data centres, and have been shown to produce orders-of-magnitude improvements in energy efficiency. Major cloud-computing providers have recently announced the deployment of FPGAs in their data centres -- a "game changer" for what was once seen as a niche technology. FPGAs are now a part of the sharing economy: from anywhere in the world, one can rent a cloud FPGA for accelerated energy-efficient custom computing. FPGAs are poised for a prominent role in energy-efficient data centre computing, however, a challenge is that they are difficult to use by software engineers for two primary reasons: 1) implementing a circuit on an FPGA has historically required knowledge of hardware design, where the circuit is described at a low level of abstraction in a hardware description language, such as VHDL or Verilog, and 2) compiling a design for an FPGA is time intensive, taking up to hours or days, preventing the real-time design -> debug -> execute iterative cycle that software engineers are accustomed to. What is needed is for FPGAs to be software programmable, with the desired behaviour specified at a high level of abstraction, and new approaches and architectures that permit such specifications to be rapidly compiled into the underlying FPGA hardware. A first thrust undertaken to address the FPGA usability challenge is the application of machine learning techniques within high-level synthesis (HLS). HLS is the automated synthesis of a hardware circuit from a software program. Presently, the quality of circuit (power, performance, area) produced by HLS tools is inferior to human-expert designed hardware. HLS tools are by nature heuristic approaches, and we propose to apply machine learning algorithms, within HLS itself, to raise circuit quality. A second research thrust concerns the architecture of the target FPGA. We propose to attack today's lengthy compile times through compile-time-friendly architectural changes.