Next-Generation Computer Aided Design Flow Challenges for Field Programmable Gate Arrays

现场可编程门阵列（fpga）是定制芯片设计的替代方案；他们可以配置，在现场，实现任何电路。现代fpga包含可配置逻辑块（clb）的可重构阵列，嵌入式硬知识产权（IP）块和可编程路由结构，并且具有每个器件最高的晶体管计数之一。他们使用同样先进的处理技术，否则只有计算机处理器公司（如英特尔，英伟达）使用。Altera和Xilinx的最新器件采用28nm工艺技术制造，晶体管数量分别为39亿个和68亿个。对于许多公司来说，fpga提供了足够的容量和速度，使公司能够“无晶圆厂”，从而避免了代工厂的昂贵和耗时的服务。**计算机辅助设计（CAD）流程用于将电路的HDL描述转换为编程位流。在这个流程中，HDL首先被合成为电路的寄存器-传输级（RTL）描述，该电路被技术映射并聚集到该设备上的特定逻辑组件中。放置阶段为这些组件分配设备上的特定位置，路由阶段确定路由结构的适当配置，以提供组件之间所需的连接。** FPGA CAD算法通常优化性能，面积和最近的功率。然而，今天这还不够。这项研究将在两个领域提供CAD算法的进展。首先，随着制程技术尺寸的减小，诸如工艺变化以及最近设备劣化减少芯片寿命等问题日益受到关注。本研究的第一部分将解决优化FPGA寿命的CAD流程。研究还表明，计算工作站的处理能力已经无法跟上FPGA设计日益复杂的步伐，造成了11倍的生产力差距。研究的第二部分将侧重于通过并行化来缩小这一差距

Field Programmable Gate Arrays (FPGAs) are an alternative to custom chip design; they can be configured, in the field, to implement any circuit. Modern FPGAs contain a reconfigurable array of Configurable Logic Blocks (CLBs), embedded hard Intellectual Property (IP) blocks, and a programmable routing fabric and have one of the highest transistor counts per device. They use the same leading-edge process technology that is otherwise only used by computer processor companies (e.g. Intel, NVIDIA). The latest devices from Altera and Xilinx are fabricated with 28nm process technology with transistor counts of 3.9 and 6.8 billion, respectively. For many companies, FPGAs provide sufficient capacity and speed, allowing the company go "fabless" to avoid the expensive and time consuming services of a foundry.** A Computer Aided Design (CAD) flow is used to transform an HDL description of a circuit into a programming bit stream. In this flow, the HDL is first synthesized into a Register-Transfer-Level (RTL) description of the circuit, which is technology mapped and clustered into the specific logic components on that device. The placement phase assigns specific locations on the device to these components and the routing phase determines an appropriate configuration of the routing fabric to provide the needed connectivity between components. ** FPGA CAD algorithms typically optimize for performance, area, and more recently power. However, today this is not enough. This research will provide advances in CAD algorithms in two areas. First, as process technology sizes decrease, issues such as process variation, and more recently device deterioration reducing the life time of chips, are increasing concerns. The first part of this research will address CAD flows that optimize for FPGA longevity. Research has also demonstrated that the processing power of computing workstations has failed to keep pace with the increasing complexity of FPGA designs, creating a productivity gap of 11x. The second part of the research will focus on reducing this gap through parallelization.**