A configurable profiling core for multicore processors

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For years, processor designers were able to fully leverage Moore's Law, which states that the density of components integrated on a single chip grows exponentially over time. In conjunction with increasing chip density, chip clock rates have previously been following a trend of doubling approximately every 18 months. However, due to the increasing power requirements of processors, this clock frequency scaling is no longer possible. Instead, processor manufacturers have moved to designing multi-core processor systems, increasing possible parallelism instead to leverage the increasing chip density while clock rates remain relatively constant. It is predicted that the number of processors in multi-core systems will eventually scale to the 10s and 100s. This becomes a significant challenge for the Operating System (OS), which has to determine how to schedule tasks effectively on these complex systems. How will the OS determine how to schedule threads so as to minimize cache contention and which processor(s) meet each task's execution requirements on heterogeneous systems? Currently a number of hardware counters are included as part of a processor's architecture that enable limited profiling of applications at run time. However, these do not provide sufficient flexibility or information to effectively guide the OS in task assignment. While existing counters report the symptoms of a problem (i.e., how large the cache miss rate is), they do not provide insight into why the problem has occurred and how it could be fixed. The proposed profiling core will provide both operating systems and applications with detailed information about run time performance bottlenecks and will enable them to address these bottlenecks via scheduling or dynamic compilation. As a result, application software will be able to better leverage the intrinsic nature of the multi-core hardware platform, be it homogeneous or heterogeneous. Furthermore, the profiling functionality will be isolated on a separate core, and this will facilitate inclusion of rich profiling functionality into new processors via IP reuse. This research project has the potential to significantly improve a customer's experience and productivity when used in conjunction with commercial multi-core processors.