Next-Generation Computer Aided Design Flow Challenges for Field Programmable Gate Arrays

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Field Programmable Gate Arrays (FPGAs) are an alternative to custom chip design; they can be configured, in the field, to implement any circuit. Modern FPGAs contain a reconfigurable array of Configurable Logic Blocks (CLBs), embedded hard Intellectual Property (IP) blocks, and a programmable routing fabric and have one of the highest transistor counts per device. They use the same leading-edge process technology that is otherwise only used by computer processor companies (e.g. Intel, NVIDIA). The latest devices from Altera and Xilinx are fabricated with 28nm process technology with transistor counts of 3.9 and 6.8 billion, respectively. For many companies, FPGAs provide sufficient capacity and speed, allowing the company go "fabless" to avoid the expensive and time consuming services of a foundry. A Computer Aided Design (CAD) flow is used to transform an HDL description of a circuit into a programming bit stream. In this flow, the HDL is first synthesized into a Register-Transfer-Level (RTL) description of the circuit, which is technology mapped and clustered into the specific logic components on that device. The placement phase assigns specific locations on the device to these components and the routing phase determines an appropriate configuration of the routing fabric to provide the needed connectivity between components. FPGA CAD algorithms typically optimize for performance, area, and more recently power. However, today this is not enough. This research will provide advances in CAD algorithms in two areas. First, as process technology sizes decrease, issues such as process variation, and more recently device deterioration reducing the life time of chips, are increasing concerns. The first part of this research will address CAD flows that optimize for FPGA longevity. Research has also demonstrated that the processing power of computing workstations has failed to keep pace with the increasing complexity of FPGA designs, creating a productivity gap of 11x. The second part of the research will focus on reducing this gap through parallelization.