Next-Generation Computer Aided Design Flow Challenges for Field Programmable Gate Arrays

现场可编程门阵列(FGA)是定制芯片设计的替代方案；可以在现场配置它们来实现任何电路。现代的现场可编程门阵列包含可配置逻辑块(CLB)、嵌入式硬知识产权(IP)块和可编程布线结构的可重新配置阵列，并且每个器件具有最高的晶体管数量之一。它们使用相同的前沿工艺技术，否则只能由计算机处理器公司(例如英特尔、NVIDIA)使用。Altera和Xilinx的最新器件采用28 nm工艺技术制造，晶体管数量分别为39亿和68亿。对于许多公司来说，现场可编程门阵列提供了足够的能力和速度，使公司可以“无厂房”，避免昂贵和耗时的代工厂服务。 计算机辅助设计(CAD)流程用于将电路的HDL语言描述转换成编程比特流。在这个流程中，硬件描述语言首先被综合成电路的寄存器传输级(RTL)描述，该描述被技术映射并聚集到该设备上的特定逻辑组件中。放置阶段将设备上的特定位置分配给这些组件，路由阶段确定路由交换矩阵的适当配置，以提供组件之间所需的连接。 FPGA CAD算法通常会针对性能、面积和最近的功耗进行优化。然而，今天这还不够。这项研究将在两个领域提供CAD算法的进展。首先，随着工艺技术规模的减小，工艺变化以及最近器件退化缩短芯片寿命等问题日益引起人们的关注。这项研究的第一部分将解决针对FPGA寿命进行优化的CAD流程。研究还表明，计算工作站的处理能力未能跟上日益复杂的FPGA设计的步伐，造成了11倍的生产率差距。研究的第二部分将重点放在通过并行化来缩小这一差距。

Field Programmable Gate Arrays (FPGAs) are an alternative to custom chip design; they can be configured, in the field, to implement any circuit. Modern FPGAs contain a reconfigurable array of Configurable Logic Blocks (CLBs), embedded hard Intellectual Property (IP) blocks, and a programmable routing fabric and have one of the highest transistor counts per device. They use the same leading-edge process technology that is otherwise only used by computer processor companies (e.g. Intel, NVIDIA). The latest devices from Altera and Xilinx are fabricated with 28nm process technology with transistor counts of 3.9 and 6.8 billion, respectively. For many companies, FPGAs provide sufficient capacity and speed, allowing the company go "fabless" to avoid the expensive and time consuming services of a foundry. A Computer Aided Design (CAD) flow is used to transform an HDL description of a circuit into a programming bit stream. In this flow, the HDL is first synthesized into a Register-Transfer-Level (RTL) description of the circuit, which is technology mapped and clustered into the specific logic components on that device. The placement phase assigns specific locations on the device to these components and the routing phase determines an appropriate configuration of the routing fabric to provide the needed connectivity between components. FPGA CAD algorithms typically optimize for performance, area, and more recently power. However, today this is not enough. This research will provide advances in CAD algorithms in two areas. First, as process technology sizes decrease, issues such as process variation, and more recently device deterioration reducing the life time of chips, are increasing concerns. The first part of this research will address CAD flows that optimize for FPGA longevity. Research has also demonstrated that the processing power of computing workstations has failed to keep pace with the increasing complexity of FPGA designs, creating a productivity gap of 11x. The second part of the research will focus on reducing this gap through parallelization.