Composable Heterogeneous Computing Systems

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As computers become more powerful, revolutionary technologies (eg Video-calling, Artificial Intelligence) are realized. However, the increased computing capacity needed to enable new disruptive technologies (eg accurate weather, genomics and materials science modelling) is not attainable using general-purpose processors due to energy constraints. Instead, heterogeneous Domain-Specific Architectures (DSAs) can provide the needed high-performance computing; but the design space is huge and complex, especially as chip fabrication technologies are moving from 2D planar designs to emerging 3D die-stacking solutions. We propose to develop an open-source, extensible, flexible experimental framework for heterogeneous systems that will allow designers to evaluate and reason about new compute architectures, runtime services and programming models. No such framework exists today, but it is essential for researchers to harness the full potential of DSAs implemented on modern technologies. Motivated by emerging applications, this program lies at the intersection of novel compilation technologies and advanced computing platforms enabled by modern fabrication technology. The proposed heterogeneous compute framework for multi-application workloads is a key first step to enable the design of these complex heterogeneous systems and provide the necessary abstractions to make them programmable by non-experts. It requires 3 components: a compilation flow, runtime support, and hardware model(s). The compilation flow needs to identify multiple mappings for individual tasks to improve runtime sharing of computing resources (CRs). When the Heterogeneous Compute Platform (HCP) includes reconfigurable hardware (e.g. an FPGA), it also needs to identify potential custom instructions and Hardware Accelerators and how they might be used and shared to improve performance and energy consumption across the application workload. Runtime services (eg an OS) are needed to schedule tasks and exploit workload CR sharing at runtime. Finally, the HCP's design complexity makes it extremely difficult to validate correctness experimentally. Hardware models that can be used to guarantee correctness of both the hardware platform and the software it executes are crucial to ensure correct operations and the validity of research results. These three components present numerous questions and challenges and form the foundation to collectively realize this DG's objective in the next five years. Combined with Dr. Shannon's pattern and process of mentoring and sponsoring her students into their future careers while ensuring and equitable, diverse and inclusive training environment, this program with the resulting framework will result in HQP with a combination of software and hardware skills that will be valuable to companies that develop next-generation compute systems and in application areas that require high-end compute solutions (e.g. biomedical and environmental technologies, defense, etc.).