Digital-intensive clocking and data recovery circuits for low-power scalable wireline transceivers

适用于低功耗可扩展有线收发器的数字密集型时钟和数据恢复电路

• 批准号: 483881-2015
• 负责人: Shekhar, Sudip
• 金额: $ 2.4万
• 依托单位: University of British Columbia
• 依托单位国家: 加拿大
• 项目类别: Collaborative Research and Development Grants
• 财政年份: 2018
• 资助国家: 加拿大
• 起止时间: 2018-01-01 至 2019-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=664992
• 关键词: Digital; intensive; clocking; data; recovery

Globally, we are on the cusp of revolutionary changes in communications fueled by the use of high throughput computing based on datacenter computers on one side, and mobile computing platforms such as laptops, tablets and smartphones on the other. Aggressive scaling of complementary metal-oxide-semiconductor (CMOS) technologies accompanied by increasing complexity of integrated-circuits has led to fast and efficient computing systems. These platforms demand off-chip data bandwidth with extremely low power consumption in order to conserve power, posing significant design challenges. This collaborative project between UBC and Intel will focus on addressing these challenges.****This proposed research aims to develop advanced wireline integrated circuits (ICs) for low-power transceivers. The work to be accomplished in this project primarily involves a mix of modelling, design and measurement work. The target application is next-generation wireline solutions and products for the industry such as MIPI M-PHY, next-generation PCIE and USB, etc.******

在全球范围内，我们正处于基于基于数据中心计算机的高吞吐量计算以及另一方面的移动计算平台（例如笔记本电脑，平板电脑和智能手机）的革命性变化的风口。互补金属 - 氧化物 - 气管导体（CMOS）技术的积极缩放伴随着综合电路的复杂性的增加，导致了快速有效的计算系统。这些平台要求具有极低功耗的芯片数据带宽，以节省功率，并带来重大的设计挑战。 UBC和英特尔之间的合作项目将专注于解决这些挑战。该项目要完成的工作主要涉及建模，设计和测量工作。目标应用程序是MIPI M-PHY，下一代PCIE和USB等行业的下一代有线解决方案和产品。******