Digital-intensive clocking and data recovery circuits for low-power scalable wireline transceivers

在全球范围内，我们正处于通信革命性变革的风口浪尖，一方面是基于数据中心计算机的高吞吐量计算的使用，另一方面是基于笔记本电脑、平板电脑和智能手机等移动计算平台的使用。互补金属氧化物半导体（CMOS）技术的积极扩展伴随着集成电路的复杂性增加，导致了快速高效的计算系统。这些平台需要极低功耗的片外数据带宽，以节省电力，这带来了重大的设计挑战。UBC和英特尔之间的合作项目将专注于解决这些挑战。****这项提议的研究旨在为低功耗收发器开发先进的有线集成电路（ic）。在这个项目中要完成的工作主要包括建模、设计和测量工作。目标应用是面向行业的下一代有线解决方案和产品，如MIPI M-PHY，下一代PCIE和USB等******

Globally, we are on the cusp of revolutionary changes in communications fueled by the use of high throughput computing based on datacenter computers on one side, and mobile computing platforms such as laptops, tablets and smartphones on the other. Aggressive scaling of complementary metal-oxide-semiconductor (CMOS) technologies accompanied by increasing complexity of integrated-circuits has led to fast and efficient computing systems. These platforms demand off-chip data bandwidth with extremely low power consumption in order to conserve power, posing significant design challenges. This collaborative project between UBC and Intel will focus on addressing these challenges.****This proposed research aims to develop advanced wireline integrated circuits (ICs) for low-power transceivers. The work to be accomplished in this project primarily involves a mix of modelling, design and measurement work. The target application is next-generation wireline solutions and products for the industry such as MIPI M-PHY, next-generation PCIE and USB, etc.******