High Performance Deep Scaled CMOS Transceivers

高性能深度扩展 CMOS 收发器

• 批准号: RGPIN-2016-06238
• 负责人: Mason, Ralph
• 金额: $ 2.08万
• 依托单位: Carleton University
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2019
• 资助国家: 加拿大
• 起止时间: 2019-01-01 至 2020-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=682984
• 关键词: Performance; Deep; Scaled; CMOS; Transceivers

The objective of this research is to advance the art of monolithic radio circuits. The author has produced circuits now in industrial production for narrow band communications. As well, he is working on broadband phased array wireless communications circuits and All Digital Phase-Lock Loop Circuits (ADPLLs) that can be used for both wireless and local area networking in computer systems. This includes the complete RF and analog radio subsystem, with work on front-end, frequency synthesis and analog/digital conversion circuits. By integrating efforts in all three areas, he can make proper tradeoffs and exploit synergies between system components.***The main focus of this effort is directed at getting high performance from low-cost deep scaled CMOS technologies with transistor channel lengths well below 100nm. Two novel technologies being developed are low power/phase noise injection locked oscillators and low jitter/high linearity subsampling circuits that can be used for receiving data and as part of a subsampling synthesizer. Most recently, these technologies have been integrated as part of millimeter wave phased array architecture and as part of an Injection Locked Rotary Travelling Wave Oscillator which provide superior performance with low power consumption. In particular, the state of the art phase noise performance of these implementations addresses one of the key limitations of high data rate wireless systems. The significance of this work will be the ability to produce low cost highly integrated CMOS transceivers with data rates capabilities to support the most demanding applications such as streaming video and gigabit wireless data networks.***One of the critical aspects of this work will be developing high frequency low phase oscillators and synthesizers which are typically the limiting factor in wireless transceivers using higher order modulation signals. Also critical is the ability to implement these circuits in deep scaled CMOS technologies and distribute their signals throughout an IC without degrading performance or greatly increasing power consumption. The author is encouraged by early results and would note that this technology has broader applications in radar systems, on-chip clock distribution networks and high performance SERDES circuits.**

这项研究的目的是推进单片无线电电路的艺术。作者已经生产了用于窄带通信的电路，目前已进入工业生产。此外，他还从事宽带相控阵无线通信电路和全数字锁相环电路（ADPLL）的研究，这些电路可用于计算机系统中的无线和局域网。这包括完整的RF和模拟无线电子系统，以及前端、频率合成和模拟/数字转换电路。通过整合所有三个领域的工作，他可以做出适当的权衡，并利用系统组件之间的协同作用。这项工作的主要重点是从低成本的深度缩放CMOS技术中获得高性能，晶体管沟道长度远低于100 nm。 正在开发的两种新技术是低功率/相位噪声注入锁定振荡器和低抖动/高线性度二次采样电路，可用于接收数据和作为二次采样合成器的一部分。 最近，这些技术已被集成为毫米波相控阵架构的一部分，并作为注入锁定旋转行波振荡器的一部分，提供了低功耗的上级性能。 特别地，这些实现的最新相位噪声性能解决了高数据速率无线系统的关键限制之一。 这项工作的重要意义在于能够生产低成本、高集成度的CMOS收发器，这些收发器具有数据速率能力，可支持最苛刻的应用，如流媒体视频和千兆位无线数据网络。这项工作的关键方面之一将是开发高频低相位振荡器和合成器，这通常是使用高阶调制信号的无线收发器的限制因素。 同样重要的是，能够在深度缩放的CMOS技术中实现这些电路，并将其信号分布在整个IC中，而不会降低性能或大幅增加功耗。作者对早期的结果感到鼓舞，并指出该技术在雷达系统、片上时钟分配网络和高性能SERDES电路中有更广泛的应用。