High Performance Deep Scaled CMOS Transceivers

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The objective of this research is to advance the art of monolithic radio circuits. The author has produced circuits now in industrial production for narrow band communications. As well, he is working on broadband phased array wireless communications circuits and All Digital Phase-Lock Loop Circuits (ADPLLs) that can be used for both wireless and local area networking in computer systems. This includes the complete RF and analog radio subsystem, with work on front-end, frequency synthesis and analog/digital conversion circuits. By integrating efforts in all three areas, he can make proper tradeoffs and exploit synergies between system components. The main focus of this effort is directed at getting high performance from low-cost deep scaled CMOS technologies with transistor channel lengths well below 100nm. Two novel technologies being developed are low power/phase noise injection locked oscillators and low jitter/high linearity subsampling circuits that can be used for receiving data and as part of a subsampling synthesizer. Most recently, these technologies have been integrated as part of millimeter wave phased array architecture and as part of an Injection Locked Rotary Travelling Wave Oscillator which provide superior performance with low power consumption. In particular, the state of the art phase noise performance of these implementations addresses one of the key limitations of high data rate wireless systems. The significance of this work will be the ability to produce low cost highly integrated CMOS transceivers with data rates capabilities to support the most demanding applications such as streaming video and gigabit wireless data networks. One of the critical aspects of this work will be developing high frequency low phase oscillators and synthesizers which are typically the limiting factor in wireless transceivers using higher order modulation signals. Also critical is the ability to implement these circuits in deep scaled CMOS technologies and distribute their signals throughout an IC without degrading performance or greatly increasing power consumption. The author is encouraged by early results and would note that this technology has broader applications in radar systems, on-chip clock distribution networks and high performance SERDES circuits.