Development of fault-tolerant flip-flops and RISC-V cores with GF 22nm FD-SOI CMOS technology

与思科系统(Cisco)合作项目的总体目标是开发容错 采用最先进的GlobalFundries(GF)CMOS22 nm全耗尽硅ON制作的逻辑电路 绝缘体(FDSOI)技术，以降低思科交换机和其他电子设备的软错误率 产品。在现代商业硅技术中，现代集成电路(IC)中的晶体管尺寸已经缩小到纳米范围。因此，集成电路变得更容易受到宇宙射线或制造材料产生的高能粒子引起的单粒子效应的影响(参见)。由粒子引起的误差通常被称为软误差。与批量技术相比，FDSOI技术在软误码率和功耗方面表现出显著的降低，这使得它们在许多工业应用中具有吸引力。该项目的主要目标是表征22 nm FDSOI工艺中的单粒子效应和噪声性能，并开发/评估冗余逻辑技术以降低数字电路中的软错误率。利用这一技术将在测试芯片中开发和制造各种容错存储元件，如触发器和逻辑门。设计的测试芯片将采用先进的22 nm FDSOI技术制造。离子束(重离子、中子和质子)将用于评估测试结构的软误差性能。调查还将使用校园内的脉冲激光设备来模拟离子撞击。此外，还将利用器件和电路级仿真工具对测试电路的性能进行建模和表征。这项研究将使我们的工业合作伙伴能够使用具有成本效益的技术优势(低功耗、高速度等)。在不影响可靠性和性能的情况下，实现了纳米级cmos技术。两名博士生和一名本科生将与硅可靠性领域的出版物一起接受该项目的培训。

The overall objectives of the collaborative project with Cisco Systems (Cisco) are to develop fault-tolerant logic circuits fabricated with the most advanced Globalfundries (GF) CMOS 22nm full-depleted silicon on insulator (FDSOI) technologies in order to reduce the soft error rate in Cisco's switches and other electronic products. The size of transistors in the modern integrated circuits (ICs) has been scaled down to the nanometer range in modern commercial silicon technologies. As a result, ICs have become more vulnerable to single event effects (SEE) induced by energetic particles from either cosmic rays or manufacturing materials. The induced errors by the particles are normally referred as soft errors. FDSOI technologies have shown substantial reduction in soft error rate and power compared to bulk technologies, which makes them attractive in many industrial applications. The project's main objectives are to characterize the single event effects and noise performance in the 22nm FDSOI process and develop/evaluate the redundant logic techniques to reduce the soft error rates in digital circuits. Various fault-tolerant storage components like flip-flops and logic gates will be developed and fabricated in a test chip with this technology. The test chip designed will be fabricated with the advanced 22nm FDSOI technology. Ion beams (heavy ions, neutron, and protons) will be used to evaluate the test structures' soft error performance. The investigation will also use an on-campus pulsed laser facility to simulate the ion hits. In addition, device and circuit-level simulation tools will be utilized to model and characterize the test circuits' performance. The research will enable our industrial partner using the cost-effective technologies with the advantages (lower power, higher speed, etc.) of nanoscale CMOS technologies without compromising reliability and performance. Two PhD students and one undergraduate student will be trained in this project alone with the publications in the silicon reliability field.