Development of fault-tolerant flip-flops and RISC-V cores with GF 22nm FD-SOI CMOS technology

采用格芯22nm FD-SOI CMOS技术开发容错触发器和RISC-V内核

• 批准号: 558348-2020
• 负责人: Chen, Li
• 金额: $ 2.44万
• 依托单位: University of Saskatchewan
• 依托单位国家: 加拿大
• 项目类别: Alliance Grants
• 财政年份: 2021
• 资助国家: 加拿大
• 起止时间: 2021-01-01 至 2022-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=721700
• 关键词: Development; fault; tolerant; flip; flops

The overall objectives of the collaborative project with Cisco Systems (Cisco) are to develop fault-tolerantlogic circuits fabricated with the most advanced Globalfundries (GF) CMOS 22nm full-depleted silicon oninsulator (FDSOI) technologies in order to reduce the soft error rate in Cisco's switches and other electronicproducts. The size of transistors in the modern integrated circuits (ICs) has been scaled down to the nanometer range in modern commercial silicon technologies. As a result, ICs have become more vulnerable to single event effects (SEE) induced by energetic particles from either cosmic rays or manufacturing materials. The induced errors by the particles are normally referred as soft errors. FDSOI technologies have shown substantial reduction in soft error rate and power compared to bulk technologies, which makes them attractive in many industrial applications. The project's main objectives are to characterize the single event effects and noise performance in the 22nm FDSOI process and develop/evaluate the redundant logic techniques to reduce the soft error rates in digital circuits. Various fault-tolerant storage components like flip-flops and logic gates will be developed and fabricated in a test chip with this technology. The test chip designed will be fabricated with the advanced 22nm FDSOI technology. Ion beams (heavy ions, neutron, and protons) will be used to evaluate the test structures' soft error performance. The investigation will also use an on-campus pulsed laser facility to simulate the ion hits. In addition, device and circuit-level simulation tools will be utilized to model and characterize the test circuits' performance. The research will enable our industrial partner using the cost-effective technologies with the advantages (lower power, higher speed, etc.) of nanoscale CMOS technologies without compromising reliability and performance. Two PhD students and one undergraduate student will be trained in this project alone with the publications in the silicon reliability field.

与思科系统公司（Cisco Systems）合作项目的总体目标是开发采用最先进的Globalfundries（GF）CMOS 22纳米全耗尽绝缘体上硅（FDSOI）技术制造的容错逻辑电路，以降低思科交换机和其他电子产品的软错误率。在现代商业硅技术中，现代集成电路（IC）中的晶体管的尺寸已经按比例缩小到纳米范围。因此，IC变得更容易受到来自宇宙射线或制造材料的高能粒子引起的单粒子效应（SEE）的影响。由粒子引起的误差通常被称为软误差。与体技术相比，FDSOI技术在软错误率和功耗方面表现出了显著的降低，这使得它们在许多工业应用中具有吸引力。该项目的主要目标是表征22纳米FDSOI工艺中的单粒子效应和噪声性能，并开发/评估冗余逻辑技术以降低数字电路中的软错误率。各种容错存储组件，如触发器和逻辑门将开发和制造在一个测试芯片与这项技术。所设计的测试芯片将采用先进的22 nm FDSOI工艺进行制作。离子束（重离子、中子和质子）将用于评估测试结构的软误差性能。调查还将使用校园内的脉冲激光设备来模拟离子撞击。此外，器件和电路级仿真工具将被用来模拟和表征测试电路的性能。该研究将使我们的工业合作伙伴能够使用具有成本效益的技术，这些技术具有优势（低功耗，高速度等）。纳米级CMOS技术，而不影响可靠性和性能。两名博士生和一名本科生将在这个项目中单独与硅可靠性领域的出版物进行培训。