Development of fault-tolerant flip-flops and RISC-V cores with GF 22nm FD-SOI CMOS technology

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The overall objectives of the collaborative project with Cisco Systems (Cisco) are to develop fault-tolerantlogic circuits fabricated with the most advanced Globalfundries (GF) CMOS 22nm full-depleted silicon oninsulator (FDSOI) technologies in order to reduce the soft error rate in Cisco's switches and other electronicproducts. The size of transistors in the modern integrated circuits (ICs) has been scaled down to the nanometer range in modern commercial silicon technologies. As a result, ICs have become more vulnerable to single event effects (SEE) induced by energetic particles from either cosmic rays or manufacturing materials. The induced errors by the particles are normally referred as soft errors. FDSOI technologies have shown substantial reduction in soft error rate and power compared to bulk technologies, which makes them attractive in many industrial applications. The project's main objectives are to characterize the single event effects and noise performance in the 22nm FDSOI process and develop/evaluate the redundant logic techniques to reduce the soft error rates in digital circuits. Various fault-tolerant storage components like flip-flops and logic gates will be developed and fabricated in a test chip with this technology. The test chip designed will be fabricated with the advanced 22nm FDSOI technology. Ion beams (heavy ions, neutron, and protons) will be used to evaluate the test structures' soft error performance. The investigation will also use an on-campus pulsed laser facility to simulate the ion hits. In addition, device and circuit-level simulation tools will be utilized to model and characterize the test circuits' performance. The research will enable our industrial partner using the cost-effective technologies with the advantages (lower power, higher speed, etc.) of nanoscale CMOS technologies without compromising reliability and performance. Two PhD students and one undergraduate student will be trained in this project alone with the publications in the silicon reliability field.