Atomic-Scale Electronics

原子级电子学

• 批准号: RGPIN-2018-05969
• 负责人: Voinigescu, Sorin
• 金额: $ 4.66万
• 依托单位: University of Toronto
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2020
• 资助国家: 加拿大
• 起止时间: 2020-01-01 至 2021-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=713972
• 关键词: Atomic; Scale; Electronics

The progression of CMOS transistors and technology is expected to reach 5nm gate length by the year 2030. At these dimensions and beyond, many of the properties of bulk materials, including the bandgap, the energy band diagrams, and carrier mobilities, undergo dramatic changes and tunneling dominates. Coincidentally, room-temperature tunneling-based coupled quantum-dot (QD) devices, envisioned for quantum computing (QC), will also become feasible at these dimensions. Although integration density has continued to follow Moore's law due to feature size shrinking and the introduction of 3D transistor structures such as the FinFET, MOSFETs are fast approaching their scaling limits. This will affect the future evolution of both computing and wireless communication, the pillars of today's revolution in data science, machine learning and the internet of things, which rely on ever-increasing computational power and data rates, and on ambient sensing. To continue computing speed and functionality improvement beyond the end of CMOS, it is critical that a variety of channel materials and qubit structures suitable for integration in a production silicon platform be thoroughly investigated for large volume and low-cost, scalable QC qubits and integrated circuits. This proposal addresses (i) the continued scaling of computational power by exploring novel atomic-scale quantum-computing (QC) hardware in CMOS foundry processes, which can be integrated on the same die with classical CMOS logic and millimeter-wave electronics, and (ii) transceiver architectures exploiting the un-chartered 140-300 GHz frequency band for qubit spin control/readout, ambient sensing, instrumentation, and wireless communications at over 100 Gb/s. The proposed qubit ICs consist of coupled-QD electron and hole spin qubits, placed in the atomic-scale channel of multi-gate n- and p-MOSFETs, and of 60-240GHz spin control and spin readout circuits integrated on the same die. As a radical breakthrough, the fabricated qubits will feature mode energy level splitting on the order of 0.25-1 meV corresponding to Rabi frequencies in the 60-240GHz range, suitable for operation at 312 degrees Kelvin, two orders of magnitude higher than today's qubits. The tuned mm-wave circuits allow for 10-20ps spin control pulses which help to filter out wideband thermal noise and make the proposed qubits and QC logic more tolerant of short spin coherence and relaxation times. Thermal noise filtering may lead to even higher temperature operation for a given energy-level splitting.

CMOS晶体管和技术的进步预计到2030年将达到5 nm栅极长度。在这些尺寸及以上，体材料的许多性质，包括带隙，能带图和载流子迁移率，经历了巨大的变化和隧穿占主导地位。巧合的是，为量子计算（QC）设想的基于室温隧穿的耦合量子点（QD）器件也将在这些尺寸上变得可行。尽管由于特征尺寸缩小和FinFET等3D晶体管结构的引入，集成密度继续遵循摩尔定律，但MOSFET正在快速接近其缩放极限。这将影响计算和无线通信的未来发展，这是当今数据科学、机器学习和物联网革命的支柱，它们依赖于不断增长的计算能力和数据速率以及环境传感。为了在CMOS结束之后继续提高计算速度和功能，关键是要彻底研究适合集成在生产硅平台中的各种沟道材料和量子位结构，以实现大容量，低成本，可扩展的QC量子位和集成电路。 该提案解决了（i）通过在CMOS铸造工艺中探索新的原子级量子计算（QC）硬件来持续缩放计算能力，其可以与经典CMOS逻辑和毫米波电子器件集成在同一管芯上，以及（ii）利用未特许的140-300 GHz频带用于量子比特自旋控制/读出、环境感测、仪器仪表、无线通信速度超过100 Gb/s。 所提出的量子位集成电路包括耦合量子点电子和空穴自旋量子位，放置在多栅极n-和p-MOSFET的原子级沟道中，以及集成在同一芯片上的60- 240 GHz自旋控制和自旋读出电路。作为一个根本性的突破，制造的量子位将具有0.25-1 meV量级的模式能级分裂，对应于60- 240 GHz范围内的拉比频率，适合在312开尔文度下工作，比今天的量子位高两个数量级。调谐的毫米波电路允许10- 20 ps的自旋控制脉冲，这有助于滤除宽带热噪声，并使所提出的量子位和QC逻辑更能容忍短的自旋相干性和弛豫时间。对于给定的能级分裂，热噪声滤波可能导致甚至更高的温度操作。