基于忆阻器的非易失性状态逻辑运算方法与实现研究

基于忆阻器的非易失性状态逻辑运算被认为是提高信息处理的速度和效率、突破传统计算机架构中冯•诺依曼瓶颈、克服存储墙问题的颠覆性技术。当前，适用于逻辑运算的忆阻器性能调控、逻辑算法的优化设计和逻辑电路理论的系统建立等问题是制约基于忆阻器的逻辑运算物理实现和实用化的关键挑战。本项目拟研制高速、低功耗、阻态窗口大、一致性好的高性能双极性和互补式忆阻逻辑器件，结合器件宏观电学特性与微观物理机制建立器件的紧凑阈值电路模型，对忆阻逻辑电路拓扑结构进行全面理论分析和物理验证，系统研究和对比实质蕴涵、时序忆阻逻辑、忆阻/CMOS混合逻辑三种运算方法，目标是得到工艺复杂度、时间复杂度和空间复杂度性能均衡、突出的器件/电路结构和完备逻辑算法，建立完善的非易失性状态逻辑运算方法和电路体系，提出存储与计算融合的非冯•诺依曼架构新思路，实现在基于忆阻的信息存储与计算融合的基础理论与关键技术方面的原始创新和突破。

Memristor based nonvolatile stateful logic computing is regarded as a promising disruptive technology to improve the efficiency of information processing, to break the von Neumann bottleneck in traditional computing architecture, and to overcome the existing Memory Wall problem. However, several critical challenges are still hindering further developments of stateful computing, such as the lack of high performance memristors, logic algorithm and systematic memristive logic circuit theory. In this project, bipolar and complementary memristors with high speed, low power consumption, high HRS/LRS ratio and good uniformity will be developed. Based on the macroscopic electric characteristics and microscopic physical mechanisms, compact threshold device model will also be built. The material implication logic、sequential stateful logic and memristor/CMOS hybrid logic methods will be investigated intensively. At the same time, the topologic structure of various memristor logic circuits will be thoroughly theoretically discussed and experimentally studied. We aim to obtain simple logic device structures and functional complete logic functions with optimized fabrication process, temporal and spatial complexity, then to establish a whole system of memristor based nonvolatile stateful logic. Our work will be an important step to realize the fusion of information storage and computing, paving the way to build next generation non von Neumann architecture for large scale parallel computing.