Research on Topological Design Tools for Structured Logic Arrays

对高度自动化的软件工具的研究仍在继续，这些工具可以产生超大规模集成电路结构的逻辑设计，这些设计通过构造是正确的。研究的重点是具有以下具体研究目标的多级布尔网络的综合：满足所有；先验；尽可能地提供RO设计规则、规范和约束；并提供不同逻辑综合技术的统一理论，包括两级逻辑极小化方法、局部变换、无关技术等。一个较长期的目标是研究这些合成技术在功能水平上的可能应用。最终目标是“硅编译”，即将给定的行为规范(例如，系统架构和指令集)自动综合成指定的目标布局技术。研究了完全微处理器综合的测试用例。

Research continues on highly automated software tools which produce VLSI-structured logic designs which are correct by construction. Emphasis in the research is on synthesis of multilevel Boolean Networks with the following specific research objectives: satisfy all ;ita priori;ro design rules, specifications, and constraints whenever possible; and provide a unified theory of disparate logic synthesis techniques, including 2-level logic minimization methods, local transformation, don't-care techniques, and others. A longer-range objective is an investigation of possible applications of these synthesis techniques at the functional level. The final goal is "silicon compilation," i.e., automated synthesis of a given behavioral specification (e.g., system architecture and instruction set) into specified target layout technologies. Test cases of complete microprocessor synthesis are studied.