Avalanche Complementary Metal Oxide Semiconductor Logic: A High Speed Differential Circuit

互补金属氧化物半导体(CMOS)技术得到了广泛的应用。然而，与诸如发射极耦合逻辑等竞争(但技术上不太可取)技术相比，CMOS逻辑电路的一个问题是操作速度低。如果电容的影响最小化，则可以提高操作速度。在第一阶段，主要研究人员通过在电压波动尽可能小的可靠性考虑因素(噪声)允许的情况下操作cmos逻辑电路来研究电容最小化。他发现了一种设计技术，可以限制逻辑电路本身产生的噪音。第二阶段的目标是从实验上验证一种创新的逻辑电路，该电路的运行速度能够比传统电路快几倍。他将布局、模拟、制造原型芯片，并测量传统(曼彻斯特)16位加法器和新型CMOS16位加法器的性能。将测量最坏情况下的传播延迟、周期时间和功率消耗。预计雪崩加法器将比传统加法器快四倍。这项建议在SBIR第二阶段的所有评估点上都得到了很高的评价，如下所示。1.完全实现了第一阶段目标，取得了很好的效果。2.这种设计技术具有重要的技术意义，很可能适用于各种CMOS电路设计。3.第二阶段的目标是适当和可以实现的。4.科学与工程素质高。5.首席调查员胜任工作能力强，过去作出了重要贡献。6.预算与第二阶段的彻底调查相称。首席研究人员的成功研究将导致高可能性的理想产品，显著更快的CMOS加法器，以及实用的CMOS电路设计技术。

CMOS (Complementary Metal Oxide Semiconductor) technology is in widespread use. However, a problem with CMOS logic circuits is low speed of operation, especially compared to competing (but less technically desirable) technologies such as Emitter Coupled Logic. Speed of operation can be increased if the effect of capacitances is minimized. In Phase I the principal investigator investigated capacitance minimization by operating CMOS logic circuits with voltage swings as small as reliability considerations (noise) will permit. He found a design technique which limits noise generated by the logic circuit itself. The objective of Phase II is to validate experimentally an innovative logic circuit capable of operating several fold faster than conventional circuits. He will layout, simulate, fabricate prototype chips, and measure the performance of a conventional (Manchester) 16-bit adder and a novel CMOS Avalanche CMOS 16-bit adder. Worst case propagation delay, cycle time and power dissipation will be measured. It is anticipated that the Avalanche adder will be four times faster than the conventional one. This proposal received high ratings on all SBIR Phase II evaluation points, which are as follows. 1. Phase I objectives were met completely with excellent results. 2. This design technique has technical importance and is likely to be applicable to a variety of CMOS circuit designs. 3. Phase II objectives are appropriate and attainable. 4. Scientific and engineering quality is high. 5. The principal investigator is highly qualified to do the work, and he has made important contributions in the past. 6. The budget is commensurate with thorough Phase II investigation. Successful research by the principal investigator will result in high likelihood of a desirable product, a significantly faster CMOS adder, as well as a practical design technique for CMOS circuits.