Memory Management in Shared-Memory Multiprocessors

这是PI对中小型共享内存多处理器设计研究的延续，其中CPU的数量从很少到几百个不等。重点是内存层次结构的管理。研究了交换机的结构特点，如多级缓存层次结构和具有存储器的互连网络。该研究的一个重要组成部分是通过跟踪驱动和综合模拟提供定性和定量评估。在多级缓存层次结构的情况下，重点是两级虚拟-真实缓存层次结构的设计和评估，包含属性对基于总线层次结构的缓存一致性和性能协议的影响，以及加速跟踪驱动仿真的技术(包含属性，跟踪减少，并行仿真)。第二个研究领域是在处理器和内存模块通过多级互连网络连接的架构中减少内存延迟的技术和架构增强。研究的第一部分认为缓存是一种可行的替代方案，并研究了改进的自失效缓存一致性方案，并将其性能和成本与先前发表的协议进行了比较。第二部分继续PI关于在互连网络的交换机中引入存储器的调查。

This is a continuation of the PI's research on the design of small to medium scale shared-memory multiprocessors where the number of CPU's ranges from a very few to several hundreds. The emphasis is on the management of the memory hierarchy. Innovative architectural features, such as multi-level cache hierarchies and interconnection networks with memory in the switches are studied. An important component of the research is providing qualitative and quantitative evaluations through trace-driven and synthetic simulations. In the case of multi-level cache hierarchies, the emphasis is on the design and evaluation of a two level virtual-real cache hierarchy, the effect of inclusion properties on the protocols for cache coherence and performance in bus-hierarchy based architectures, and on techniques for speeding up trace driven simulation (inclusion properties, trace reduction, parallel simulation). A second area of research is techniques and architectural enhancements to reduce the memory latency in architectures where processors and memory modules are connected by a multi-stage interconnection network. The first part of the research considers caching as a viable alternative and studies improved self-invalidation cache coherence schemes and compares their performance and cost with those of previously published protocols. The second part continues the PI's investigation of the introduction of memory in the switches of the interconnection network.