RIA: Synthesis of Analog Circuit Layouts

本研究的目的是寻找合成的基本算法 模拟集成电路布局从原理图。 述算法使用 灵敏度驱动的基于图形的方法。 一套算法使用 电路性能对电阻和 电容布局寄生效应、热梯度和制造 处理梯度以确定电路的相对位置 元素 另一组算法生成物理布局 使用敏感性数据。 这些使用加权约束图 该方法已被用于IC布局紧凑。 图形 从灵敏度数据确定权重和约束。 一个 然后，图的适当解产生模拟电路 布局 模拟电路的布局仍然是由熟悉 符合电路、系统和制造要求。 的10%左右 50%的完全定制设计和80%的 印刷电路板设计包含模拟电路。 本研究 解决了模拟设计中的基本需求： 电路元件的布局，以及P.I.正在解决重要的 这一领域尚未解决的问题。 新颖之处在于利用了 分析以确定芯片上组件的相对位置。 首席研究员是一位有前途、有能力的年轻教授 他们应该为这个领域做出重大贡献。

This research is on finding fundamental algorithms for synthesizing analog integrated circuit layouts from schematics. The algorithms use sensitivity-driven, graph-based methods. One set of algorithms uses the sensitivity of the circuit's performance to resistive and capacitive layout parasitics, thermal gradients, and fabrication process gradients to determine the relative positions of the circuit elements. Another set of algorithms generates the physical layout using the sensitivity data. These use a weighted constraint graphs approach that has been utilized in IC layout compaction. The graph weights and constraints are determined from the sensitivity data. An appropriate solution of the graph then yields the analog circuit layout. Layouts for analog circuits are still hand crafted by experts familiar with the circuit, system and manufacturing requirements. About 10% of application-specific designs, 50% of full custom designs and 80% of printed circuit board designs contain analog circuits. This research addresses a fundamental need in analog design: automation of the layout of circuit elements, and the P.I. is addressing important unsolved problems in this area. The novelty is in using a sensitivity analysis to determine relative placement of components on the chip. The principal investigator is a promising and competent young professor who should make significant contributions to the field.