Workshop on Packaging, Interconnects, Optoelectronics for the Design of Parallel Computers; March 18-19, 1992; Schaumburg, Illinois

该奖项为一个研讨会提供部分资金，以获得实施高性能并行机的当前最先进的计划。对于大型高速并行系统，计算机设计者面临的问题必须从体系结构和互连的角度加以解决。机器和包装工程师必须通力合作，以便在完成硬件布局之前确定和解决与时钟分配、布线和分区有关的问题。评估了互连和封装对并行度和时钟速度的影响。此外，研讨会还讨论了与电路板、芯片面积限制、信号降级、互连的电磁建模和仿真、CAD仿真、光学计算及其对机器性能的影响等相关主题。研讨会领域包括微电子封装、光电子学、机器体系结构、处理器设计、VLSI和CAD，主题分为三个领域之一：(1)电子封装和互连；(2)光电子和光学技术；(3)机器体系结构。

This award provides partial funding for a workshop to access current state-of-the-art schemes for implementation of high- performance parallel machines. For large high-speed parallel systems, the problems facing the computer designer must be addressed from both the architecture and the interconnection perspective. Machine and packaging engineers must work in concert in order to identify and solve the issues pertaining to clock distribution, routing, and partitioning before the hardware layout is done. The effects of interconnects and packaging on parallelism and clock speed are evaluated. Also, the workshop addresses subjects related to board, chip area constraints, signal degradation, electromagnetic modeling and simulation of interconnects, CAD simulation, optical computing, and their effect on machine performance. Workshop areas include microelectronics packaging, optoelectronics, machine architecture, processor design, VLSI, and CAD with topics grouped into one of three areas: (1) Electronics Packaging and Interconnects; (2) Optoelectronics and Optical Technologies; (3) Machine Architecture.